Lam Research Kiyo(R) F Series Enables Critical Conductor Etch for Advanced Memory

FREMONT, CA--(Marketwired - May 13, 2015) - Lam Research Corp. (NASDAQ: LRCX), a major global supplier of innovative wafer fabrication equipment and services to the semiconductor industry, today announced its Kiyo® F Series conductor etch system is enabling the transition of 3D NAND and advanced DRAM into volume production. Key etch requirements for these applications include achieving tight critical dimension (CD) uniformity and control for 3D NAND and uniform etch depth for DRAM. Leveraging proprietary Mixed-Mode Pulsing (MMP) technology, the Kiyo F Series delivers the performance needed for advanced memory applications while maintaining high productivity. As a result, the product has won numerous critical etch market positions for advanced memory and other technology inflections, which is leading to additional market share gains.

"For 3D NAND, our customers face significant challenges in addressing difficult etch requirements, meeting aggressive production ramps, and achieving the cost benefits they need to make the transition from planar NAND," said Vahid Vahedi, group vice president, Etch Product Group. "We are collaborating closely with them to address these new challenges and to enable this inflection by delivering robust, timely solutions without compromising productivity."

By stacking memory cells vertically, NAND flash manufacturers can pack more storage capacity onto a smaller device, ease lithography requirements, and reduce manufacturing cost per bit. For multilayer 3D NAND structures, critical conductor etch processes include staircase etch and high aspect ratio (HAR) mask open for vertical channels. This mask open is crucial since it defines the CD and CD uniformity for subsequent etching of the vertical transistor channels. For staircase etch, equal-width "steps" are created at the edge of each dielectric-film pair throughout the 3D stack to form a staircase-shaped structure. Because of extensive repetition of these steps during device processing, etching at high throughput with stringent process control is vital. CD variability must be tightly managed since wordline contacts may otherwise miss landing on a step that is too narrow or uneven. For advanced DRAM devices, depth control is a key parameter, particularly for HAR front-end-of-line silicon etch applications. Concerns include aspect ratio loading, where etch rates vary because of differences in feature dimensions, and depth loading, where different etch depths may occur due to pattern density variations.