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[PUSHERKING]

Das ist die MIPS HP !

http://www.mips.com/devTools/devMembers/Spatializer.html


Nun schlaft schön weiter.

Gruß
andy

[PUSHERKING]

Die BASIS für SPAZ:
Spatializer Audio Laboratories and MIPS Technologies Align to Provide MIPS32 and MIPS64-based Designers with Advanced Audio Enhancement Technologies, Santa Clara, California, 10/3/00.

Die letzte News von MIPS

MIPS32 and MIPS64 Architectures Enhanced for Next Generation of Embedded Designs for the Internet Age
MONDAY, OCTOBER 15, 2001 9:05 AM
- BusinessWire

SAN JOSE, Calif., Mic Forum (BUSINESS WIRE) -- Oct. 15, 2001--MIPS Technologies, Inc. (Nasdaq:MIPS) today announced a series of new enhancements to its industry-standard MIPS32(TM) and MIPS64(TM) microprocessor RISC architectures. The new enhancements will increase processor efficiency and performance while cutting system power and costs in future implementations. As the foundation for next-generation MIPS-based(TM) processor-related development, the enhanced architectures will support all legacy IP (intellectual property) and will be fully compatible with the extensive lineup of third party tools, operating systems (OSs) and application software supporting the MIPS(R) architecture.

"The number and functionality of embedded categories continues to evolve," said Victor Peng, vice president of engineering for MIPS Technologies. "In response to that growth, we work with our architecture licensees to enhance the MIPS architecture to meet and exceed their projected processor needs for the applications of the future. Our licensees value MIPS32 and MIPS64 architectures as the only open, scalable microprocessor architectures with fast, seamless upgrades from 32- to 64-bits. These latest enhancements will continue to assure our architectural leadership and enable our licensees to deliver the highest level of efficiency and performance to their OEM customers."

"These latest processor architecture extensions from MIPS Technologies will be highly beneficial for adopting the MIPS embedded architecture for real-time applications," said Markus Levy, a senior analyst at MicroDesignResources. "Furthermore, the new bit manipulation instructions will directly benefit packet processing in sophisticated network systems."

Enhanced MIPS32 and MIPS64 architectures assure increased efficiency and performance on a seamless path from 32- to 64-bits, while reducing power and lowering the cost of MIPS-based systems. New architectural enhancements include:

-- Reduced interrupt latency: Interrupt processing will be faster and more efficient with general-purpose register (GPR) shadow sets, which will eliminate the need to save and restore GPRs when servicing an exception or interrupt. The shadow sets will reduce interrupt latencies by reducing register save time to just a pipeline flush.

Vectored interrupts are an additional enhancement to the architectures. They minimize the processing required to determine the interrupt cause prior to interrupt handling. Vectored interrupts can save up to 20 cycles, significantly decreasing interrupt latency and increasing a processor`s capability to manage millions of interrupts per second. This additional speed and efficiency will be welcome in most designs, particularly high-performance network applications, set-top boxes and embedded automotive controls.

-- Enhanced bit-field manipulations: These will improve performance by allowing efficient manipulation of bits within data packets and/or device registers. Bit field and other processing functions can be greatly accelerated by faster insert and extract fields, rotate and byte swap. This will enhance performance in all embedded designs, especially embedded control (such as hard disk drives), and high-speed communications using TCP/IP or other communication protocols.

-- Enhanced coprocessor support will allow fully functional MIPS64-compliant coprocessors, such as floating processor units (FPU), to be combined with a 32-bit central processing unit (CPU), thereby cutting the cost of demanding applications by teaming the optimum mix of CPU and coprocessor.

-- Expanded memory management unit (MMU): An enhanced MMU will be capable of managing pages as small as 1KB or as large as 256MB. Support for smaller page sizes benefits both memory-constrained applications such as smart mobile devices and larger network applications where page size granularity is becoming a problem. Very large page support allows entire regions of virtual memory to be mapped with a single translation lookaside buffer (TLB) entry allowing, for example, network applications to map and protect an entire memory resident database.

-- Enhanced control of caches: The evolving complexity of memory hierarchy demands additional standardization support in future (OS) implementations. MIPS Technologies is addressing this need by defining a mechanism in the architecture to indicate the presence and characteristics of L2 and L3 caches.

The new architectural enhancements will simplify and standardize the underlying mechanisms that will be used in supporting real-time software, assuring the continued availability and investment protection of standard development tools, operating systems and applications for MIPS-based solutions. This also will lower costs and speed the development of new tools for the MIPS processor market.

Availability:
The MIPS32 and MIPS64 architectures with these enhancements are available for licensing today. The first implementation from MIPS Technologies, an ultra-low-power 32-bit core, will follow in the first half of 2002.

Industry Quotes
"Alchemy Semiconductor has achieved industry-leading results in high performance, low power with the Au1000 and Au1500 integrated processor products, implementing the MIPS32 architecture. These latest enhancements will enable Alchemy to scale delivered performance even higher, while decreasing power dissipation. Alchemy actively participates in the architectural definition and specification of these enhancements."

-- Phil Pompa, Vice President of Marketing, Alchemy Semiconductor, Inc.

"ATI is pleased to have participated in the definition of these latest enhancements to the MIPS architecture. As a leading provider of multimedia chipsets, the flexibility to accelerate the processing of new graphics and media formats is critical to ATI, and these new MIPS architectural enhancements will allow us to scale future designs to higher performance levels."

-- Daniel Eiref, Director of Technology and Marketing, Consumer Products Group., ATI Technologies, Inc.

"Broadcom welcomes the introduction of these latest enhancements to the MIPS32 and MIPS64 architectures. Broadcom has participated in driving architectural features that not only considerably enhance the performance and scalability of our broadband processor products, but also enable the use of deeply embedded cores in a very flexible fashion. The MIPS architecture continues to be the right choice for Broadcom because of its strong emphasis on accelerating networking and related applications."

-- Rich Nelson, Senior Director of the Broadband Communications Business Unit, Broadcom

"As the leader in third party embedded development tools, Green Hills Software was the first commercial tools supplier to fully support and endorse the MIPS32 and MIPS64 architectures. We are pleased to have been involved with the MIPS Technologies engineering team as these enhancements were being defined. Our RTOS and compiler engineering teams applaud the enhancements, especially the reduced interrupt latency, MMU programmability and bit map manipulations. These enhancements will make our RTOSs and customer applications run faster, and simplify our life supporting the MIPS architectures."

-- John Carbone, Vice President of Marketing, Green Hills Software, Inc.

"We are very excited about these latest enhancements to the MIPS32 and MIPS64 architectures. LSI Logic is focused on providing the very highest performance SoC solutions for our Communications, Consumer and Storage customers, and we have long relied on MIPS Technologies to provide the industry`s most powerful licensable processor architectures to incorporate into our customers` SoC designs. These latest improvements to interrupt handling, bit manipulation, and memory management will further improve the performance of many of our customers` end applications."

-- Rafi Kedem, Senior Director of Processor Cores, LSI Logic Corporation

"In tandem with its new processor architectures, MIPS Technologies continues to offer state-of-the-art deployment technologies, including co-verification, that are critical to streamlining the system verification process. Our long-term relationship with MIPS Technologies has helped us provide advanced co-verification technologies in parallel with new architecture announcements."

-- Serge Leef, General Manager, System-on-Chip Verification Division, Mentor Graphics Corporation

"In the highly competitive device market, OEMs are looking to develop more powerful Windows CE-based devices at a cost-effective price. The enhancements that MIPS Technologies is making to its architecture will help enable OEMs to meet this demand, allowing them to more quickly and easily bring to market their Windows Powered smartmobile devices."

-- Keith White, Sr. Director of Marketing, Embedded and Appliance Platforms Group, Microsoft Corporation

"NEC Corporation has utilized the MIPS architecture in developing a broad range of silicon products that scale from high-performance microprocessors to power-efficient ASIC cores and application-specific products in networking, mobile and consumer markets. NEC supports the flexibility of the MIPS32 and MIPS64 architecture and its new enhancements and has contributed to the specification of this standard architecture."

-- Masahide Takada, Chief Manager, Microcomputer Division, NEC Corporation

"Philips Semiconductors develops a broad product line of MIPS-based cores and application-specific silicon for consumer, networking and mobile applications. The MIPS32 and MIPS64 instruction-set architectures provide standards for binary compatibility for application- and kernel-level software routines. These enhancements to MIPS32 and MIPS64 will be important optimizations for many critical embedded tasks: fast interrupt handling and context switching, bit manipulation and new system coprocessor features extend the MIPS architecture into demanding new applications, where directed performance and flexibility at the implementation level are key."

-- Bart de Loore, General Manager, ReUse Technology Group, Philips Semiconductors

"PMC-Sierra has driven the adoption of the MIPS architecture in many networking equipment markets. PMC-Sierra`s RM9000x2 1-GHz dual processor provides industry-leading performance for super high-end switching and routing products. These latest enhancements to the MIPS architecture will enable even greater performance scaling and faster context switching and interrupt response in future MIPS-based implementations."

-- Tom Riordan, Vice President and General Manager, MIPS Processor Division, PMC-Sierra

"Red Hat has worked closely with MIPS Technologies and its licensees to help create new solutions for consumer electronics, datacom/telecom, and office automation applications. We believe that the new enhancements can help improve performance for certain applications, and expect that they can be supported across all of our MIPS-based offerings, GNUPro, eCos, and Embedded Linux, in the future."

-- Michael Tiemann, Chief Technology Officer, Red Hat, Inc.
"SandCraft is actively working with MIPS Technologies to evolve the MIPS32 and MIPS64 architectures in order to meet the high-performance and integration requirements of our products. Our customers are demanding new features, particularly in the networking segments, that can best be met with these enhancements. Developing a balanced architecture is essential and MIPS Technologies is pushing hard to enable this."

-- Dominic McCarthy, Vice President of Architecture, SandCraft, Inc.

"Toshiba Corporation welcomes these enhancements to the MIPS32 and MIPS64 architectures. Support for faster interrupt handling and manipulation of bit fields improves code efficiency, and will allow Toshiba to develop flexible core implementations of the MIPS architecture for digital consumer, automotive and networking applications. Toshiba is pleased to have worked with MIPS Technologies in the definition of these enhancements."

-- Yutaka Murao, Senior Manager, RISC Technical Marketing Department, Microprocessor Division, Toshiba Corporation Semiconductor Company

"Through our Center of Excellence program with MIPS Technologies, Wind River has been able to provide comprehensive embedded software and development tool support for MIPS32 and MIPS64 architectures. Wind River is pleased with the new enhancements to these popular architectures and will work closely with MIPS Technologies to support new features where possible with the Tornado 2 integrated development environment and market-leading VxWorks real-time operating system."

-- David Sheaffer, Sr. Director of Marketing and Business Development, Platforms Business Unit, Wind River Systems, Inc.

About MIPS Technologies
MIPS Technologies, Inc. is a leading provider of industry-standard processor architectures and cores for digital consumer and network applications. The company drives the broadest architectural alliance that is delivering 32- and 64-bit embedded RISC solutions. The company licenses its intellectual property to semiconductor companies, ASIC developers and system OEMs. MIPS Technologies and its licensees offer the widest range of robust, scalable processors in standard, custom, semi-custom and application-specific products. The company is based in Mountain View, Calif., and can be reached at [phone] or www.mips.com.

Note to Editors: MIPS(R) is a registered trademark, and MIPS32(TM), MIPS64(TM) and MIPS-based(TM) are trademarks of MIPS Technologies, Inc. in the United States and other countries. All other trademarks referred to herein are the property of their respective owners.

CONTACT: MIPS Technologies, Inc.
Lee Garvin Flanagin, 650/567-5180
[e-mail]

[PUSHERKING]

Dieser Klick ist es:

http://www.mips.com/SearchEngine.html

gruß an die LONGS

[Michiko]

Hoffentlich geht´s nicht wie vorgestern:
Gute News, Kurs hoch. Ein oder zwei Tage keine News, Kurs wieder runter!

[PUSHERKING]

Auch Texas Instrument schläft nicht:
Zur Erinnernung:
Spatializer Audio Laboratories Inc. Expands Audio Enhancement Support to the Texas Instruments TM320C55x DSP Generation

Hier mal etwas Neues von TI:
Octiv Joins Texas Instruments Third Party Network; OctiMax Music Dynamics Processor & OctiVox Voice Dynamics Processor Now eXpressDSP Compliant on TMS320C54x DSP Generation
TUESDAY, OCTOBER 16, 2001 6:14 AM
- BusinessWire

BERKELEY, Calif., Oct 16, 2001 (BUSINESS WIRE) -- Continuously improving the digital audio experience, Octiv, an innovator in audio dynamics processing, announces that it has become a member of the Texas Instruments third-party network. In addition, Octiv`s principal products, OctiMax, for digital stereo music, and OctiVox, for monaural voice, are now eXpressDSP-compliant on the power-efficient TMS320C54x(TM) DSP generation.

Combining Octiv dynamics processing software with TI DSPs enables, for the first time, professional audio techniques as an embedded function in consumer electronics and telephony products. These dramatic improvements in audio quality require limited DSP processing power, and are easily integrated and complement existing codecs or other processing applications.

Octiv processing solves everyday audio problems.
Television viewers do not need to be blasted by loud commercials or uncomfortable shifts in loudness when channel surfing. Music fans can intermix MP3s, CDs, radio or Internet streams with consistent audio quality. Packet-switched telephony products and services can deliver more intelligible calls. Conference call participants no longer need to struggle to hear some speakers while asking another to speak more softly. Improvements are especially beneficial to mobile devices such as cell phones, PDAs, MP3 players and car audio systems where ambient noise impairs the listening experience.

Importance of joining TI`s third party network
"Joining the TI third party network is a strategic step in bringing Octiv audio innovation to manufacturers of consumer electronics, telephony, wireless and other portable devices," stated Keith McMillen, President/CEO of Octiv. "These companies rely upon Texas Instruments for the best of breed DSP applications and Octiv is already working with key TI customers."

"Adding Octiv to our third-party network will provide innovative audio technologies to a wide range of focused manufacturers," said Ray Wagstaffe, third party network worldwide manager, TI. "Working with the network members, our customers are assured access to the newest technologies that support their Texas Instruments DSP solutions."

About OctiMax Music Processor and OctiVox Voice Processor
Both products implement multi-stage, multi-band dynamics range processing for digital audio. Both include a spectral normalization algorithm that provides a time-varying level change to the audio signal in different frequency bands, in order to maximize the clarity and listen-ability of all audio sources. OctiMax is optimized for stereo music, and OctiVox is optimized for mono speech. Customization is readily available using the "preset" feature that enables customers to select optimized settings for different environments, styles of music and listening preferences.

About the TI Third Party Network
The TI TMS320(TM) third-party program is the most extensive collection of global DSP development support in the industry, with more than 400 independent companies and consultants providing TI`s customers with a broad range of application software, development hardware and software and consulting services. For more information on the TI third party program, please visit http://www.dspvillage.ti.com.

About Octiv
Octiv is improving the digital audio experience. The company offers a complete line of embedded and desktop dynamic processing software enhancements that dramatically improve the quality and performance of digital audio for consumer electronics, packet switched telephony systems and Internet media.

Based in Berkeley, Calif.-based Octiv was founded in January 2000 by a group of experienced audio industry professionals. The company has received financial backing from 3i, FG II Ventures, Novus Ventures and Intel. Additional information can be found on the Octiv Web site, http://www.octiv.com.

[karo1]

Hallo Andy, Octiv scheint eher ein "entfernter Mitbewerber" von SPAZ zu sein oder!? weiss aber nichts ausser von der PR.

MIPS hört sich gut an.

Karo

[PUSHERKING]

Infos zu MIPS
Eureka Technology Joins MIPS Alliance Program with IP Support for SoC Designs
THURSDAY, OCTOBER 18, 2001 12:03 PM
- BusinessWire

LOS ALTOS, Calif., Oct 18, 2001 (BUSINESS WIRE) -- Eureka Technology Inc., a leading intellectual property (IP) provider, today announced that it has joined MIPS Technologies` (Nasdaq:MIPS)(Nasdaq:MIPSB) MIPS(TM) Alliance Program (MAP), and further announced the availability of several IP cores designed specifically to support the industry-standard MIPS32(TM) 4K(TM) and MIPS64(TM) 5K(TM) families of processor cores.

"We are very excited about becoming a member of the MAP program and the addition of the new IP cores for use in creating new highly-integrated MIPS-based(TM) processors," said Simon Lau, President of Eureka Technology. "Eureka Technology has been focusing on system-on-chip (SoC) design with support for most popular embedded CPUs for a wide range of applications. These new cores provide risk-free and readily available design solutions to our customers who are using the MIPS processor architecture."

The new IP cores support the MIPS EC(TM) Interface for embedded processor cores as well as the SysAD bus for compatibility with existing OEM designs using MIPS-based CPUs. Eureka`s cores include CPU bus slave, PCI bridge, SDRAM controller, and system controller, which is an all-in-one companion chip to the MIPS processor. These IP cores support many advanced features of the EC and SysAD interfaces, such as address pipeline and out-of-order execution. Each of these cores is pre-verified and can be used in a stand-alone format or integrated with other Eureka IP cores for different applications. These cores are available for licensing in Verilog and VHDL source code format, and in netlist format supporting most popular FPGA and PLD devices.

"Using pre-verified IP cores substantially shortens the time-to-market for today`s SoC designers," said Kevin Meyer, vice president of marketing at MIPS Technologies." We are very pleased that Eureka Technology is offering silicon-proven IP cores that are designed specifically to support the MIPS architecture. Pre-verified cores contribute to the success of our customers` programs."

The MIPS Alliance Program (MAP) provides its members with sales and technical assistance as well as broad marketing support such as Internet and traditional marketing and promotional activities. MAP members are third-party vendors who provide complete solutions around MIPS Technologies processors. MIPS-based processors are found in digital entertainment devices such as set-top boxes and game consoles, consumer electronics, office automation machines and communications/networking equipment such as routers and servers.

Detail product information of these IP cores is available from the Eureka Technology web site at http://www.eurekatech.com

About Eureka Technology
Eureka Technology is a leading intellectual property (IP) provider for ASIC and FPGA designers. The company offers a wide range of silicon-proved system core logic functions and peripheral functions for systems based on PCI bus and various embedded CPUs including the MIPS32 and MIPS64 CPU cores. These IP cores are designed to improve the design time-to-market delay, eliminate design risks, and reduce development costs. Founded in 1993, the company has a strong customer base in the United States, Japan and Europe. For more information about the company, please visit the Web site at http://www.eurekatech.com or send email to [e-mail].

[PUSHERKING]

DAS WIRD PASSIEREN


von 0,35 auf 3,18
exakt das wird SPAZ machen
cu
andy

[PUSHERKING]

http://chart.bigcharts.com/bc3/quickchart/chart.asp?symb=sft…

[Diagonale]

Hallo zusammen

Wünsche allen SPAZen ein gepflegtes Wochenende.

Diagonale

[DNAPSPAZ]

Hi Diagonale,

erst wieder im Januar 2002,dann aber zu $.05

Liegt jetzt (fast) alles in DNAP,ist auch eine kleine Klitsche - nur das Kursziel ist anders.

cu Croko - bis bald...

[Michiko]

Aller guten Dinge sind drei!

Schönes WE Euch beiden!

Und mucho viel Grün!!

Michi

[PUSHERKING]

Richtig viel Umsätze am Freitag.
Alles wird Gut


Andy ist mal wieder LONG
EHRLICH !