Astera Labs Joins Arm Total Design to Accelerate Custom AI Infrastructure Solutions
Collaboration addresses growing rack-scale infrastructure demands with custom AI chiplet architecture connectivity solutions
SAN JOSE, Calif., Oct. 14, 2025 (GLOBE NEWSWIRE) -- Astera Labs, Inc. (Nasdaq: ALAB), a leader in semiconductor-based connectivity solutions for rack-scale AI infrastructure, today announced it has joined Arm Total Design, a comprehensive ecosystem dedicated to accelerating and simplifying custom SoC development based on Arm Neoverse Compute Subsystems (CSS). This collaboration will combine Astera Labs' Intelligent Connectivity Platform ecosystem with Arm Neoverse CSS to enable chiplet solutions that meet the growing demand for custom AI infrastructure.
The complex integration requirements of rack-scale AI infrastructure are driving a shift toward chiplet-based designs. As AI workloads demand increasingly specialized processing capabilities, traditional monolithic chip designs are hitting yield and cost limitations at advanced process nodes, creating demand for more flexible architectures. Chiplet architectures enable AI platform developers to combine diverse processing units—including Arm compute subsystems alongside memory, networking, and acceleration components—into unified systems optimized for different functions. This modular approach achieves faster time-to-market through validated, reusable components while delivering the flexible, heterogeneous integration capabilities required by next-generation AI infrastructure.
As a key design services partner in Arm Total Design, Astera Labs will provide multi-protocol chiplet capabilities through its Intelligent Connectivity Platform, offering comprehensive PCIe, Ethernet, CXL, and UALink connectivity solutions that enable customers to build custom AI infrastructure with validated, interoperable connectivity from day one. Astera Labs' proven ability to deliver first-to-market interconnect solutions, combined with extensive validation through the company's Cloud-Scale Interop Lab, fast-tracks customer designs from development to production, while reducing qualification risk. The collaboration combines Arm's compute subsystem expertise with Astera Labs' proven connectivity leadership, and aims to accelerate time-to-market, while supporting open standards-based platforms that leverage broad innovation, interoperability, and diverse multi-vendor supply chains.

