IDTechEx Explores the Role of 3D Cu-Cu Hybrid Bonding in Powering Future HPC and AI Products - Seite 2

Three ways of Cu-Cu hybrid bonding

There are three primary methods for achieving hybrid bonding: die-to-die (D2D), die-to-wafer (D2W), and wafer-to-wafer (W2W). Each approach offers distinct advantages and disadvantages, influencing its suitability for various applications.

Die-to-Die bonding offers the highest assembly yield since both dies can undergo individual testing before bonding. This method also provides the highest design flexibility. However, it suffers from very low throughput and presents significant challenges during the process, particularly regarding edge effects, contamination, and particles introduced during singulation. Additionally, die-to-die bonding requires pick & place equipment with exceptionally high accuracy. Due to these manufacturing challenges and low throughput, this method currently has limited commercial use in hybrid bonding applications.

Wafer-to-wafer bonding stands out for its highest throughput, which is crucial in the semiconductor industry. Its process steps are simpler compared to die-to-die bonding, as it eliminates the need for cutting dies and pick and place procedures. However, wafer-to-wafer bonding may result in lower yield and reduced design flexibility, as the top and bottom dies must be the same size. Despite these drawbacks, wafer-to-wafer bonding remains the most commonly employed approach for Cu-Cu hybrid bonding in current commercial applications.

Die-to-wafer bonding occupies a middle ground between die-to-die and wafer-to-wafer methods. This approach provides higher design flexibility and yield compared to wafer-to-wafer bonding. However, it faces challenges related to lower throughput and more complex processing requirements. Despite these challenges, die-to-wafer bonding has gained momentum due to its ability to strike a balance between design flexibility and manufacturing efficiency.

Overall, the choice of hybrid bonding method depends on factors such as assembly yield requirements, design flexibility, throughput considerations, and processing challenges. Each approach offers distinct trade-offs, shaping its applicability in semiconductor packaging and integration.

How hybrid bonding is implemented in HPC chips

The most prominent adoption of hybrid bonding is AMD employing TSMC's 3D SOIC (hybrid bonding) technology for stacking L3 cache die onto a computing chip in two product lines: the consumer AMD Ryzen 7000X3D CPU for desktops (incl. AMD Ryzen 9 7950X3D and AMD Ryzen 7 5800X3D) and the EPYC processor for high-performance computing (HPC). AMD emphasizes hybrid bonding's role in surpassing their power efficiency goals with chiplet and 3D-enabled architecture. They highlight its superiority over micro bump 3D technology, citing 15 times higher interconnect density and 3 times greater energy efficiency. Other examples include Graphcore's Bow Intelligence Processing Unit (BOW) is the world's first 3D Wafer-on-Wafer (WoW) processor, utilizing TSMC 7 nm technology and TSMC 3D SoIC technology for a 3D die, featuring 1,472 IPU-Core tiles with 900MB of in-processor memory, offering up to 40% faster AI performance and 16% better performance-per-Watt compared to its 2D predecessor. Another key example is the utilization of hybrid bonding in high-bandwidth memory (HBM). Major players in the HBM market, such as SK Hynix, Samsung, and Micron, are increasingly exploring hybrid bonding for their applications. While microbump stacking has been the traditional method in HBM, the growing demand for enhanced bandwidth expansion and power efficiency is driving the active investigation of hybrid bonding. The commercialization of hybrid bonding-based HBMs is expected in the next generation or thereafter, offering a substantial competitive advantage over microbump-based alternatives. This provides these competitors with a strong edge against the current market leader.