GBT Received a Notice of Allowance for its Microchip Reliability Verification and Auto-Correction Patent Application

The patent application covers a ML-Driven technology to detect and correct microchip’s reliability violations, particularly for advanced nanometer nodes

SAN DIEGO, June 06, 2023 (GLOBE NEWSWIRE) -- GBT Technologies Inc. (OTC PINK: GTCHD ) ("GBT” or the “Company”), received a notice of allowance for its microchip’s reliability verification and auto-correction electronic design automation (EDA) patent application, which has been assigned internal project’s code name, Epsilon.

As integrated circuits (ICs) manufacturing node is constantly scaling down, design firms are facing a broad spectrum, complex challenge in the electrical reliability domain, which is dictated by the laws of physics. Microchip reliability refers to the ability of an IC to perform its intended functions accurately and consistently over its operational lifetime. It encompasses the chip's ability to operate within specified parameters, without degradation or failure, under various environmental conditions and stresses. High performance computing systems require optimal electrical and thermal characteristics to ensure reliability and accuracy.

Advanced ICs are the core of these systems and need to function with a high level of dependability. Particularly in the fields of medicine, aviation, transportation, data storage and communication, a microchip’s reliability factor has become a crucial factor. Addressing a microchip reliability becomes particularly crucial as the scale of the ICs decreases to low nanometer dimensions. With smaller feature sizes, more complex reliability challenges emerge, including electromigration, process variations and others.

GBT’s Epsilon patent application introduces innovative technology with the goal of addressing advanced semiconductor node’s physics providing a high level of reliability, optimal thermal design, lower power consumption and high performance. The described technology includes machine learning algorithms to enable robust design, process optimization, characterization, modeling and simulation. The technology underling the patent application identifies reliability flaws, describes the found issues, and enables an automatic correction of these reliability issues, early during the IC’s design phase.