ASE launches its Integrated Design EcosystemTM to enable silicon package design efficiencies that reduce cycle time by half

Advanced Semiconductor Engineering, Inc. (ASE), a member of ASE Technology Holding Co., Ltd. (NYSE: ASX, TAIEX: 3711), today announced the launch of its Integrated Design Ecosystem^TM (IDE), a collaborative design toolset optimized to systematically boost advanced package architecture across its VIPack^TM platform. This innovative approach allows a seamless transition from single die SoC to multi-die disaggregated IP blocks including chiplets and memory for integration using 2.5D or advanced fanout structures. ASE’s IDE enables design efficiencies up to 50% and sets new standards for quality and user experience. Integrating novel package design tool capabilities into ASE’s workflow has resulted in significant cycle time reduction while lowering customer costs.

Enhanced features of IDE include cross platform interaction encompassing layout and verification, advanced RDL and silicon interposer auto routing with embedded design rule checking (DRC), and Package Design Kit (PDK) implementation in the design workflow. As an example, a critical milestone has been achieved for a Fan Out Chip on Substrate - Chip Last (FOCoS-CL) package where the design cycle timeline has been substantially reduced from 90 days to 45 days.

Today’s semiconductor technology roadmaps comprise complex performance requirements that are driving advanced packaging trends, yet present unique package design challenges. Frontline chiplet and heterogeneous integration developments are emerging to push technology boundaries and are elevating demand for innovative design flows and circuit-level simulations to accelerate complex design achievements. The IDE has been launched by ASE to address design challenges of its VIPack platform technologies and extensively improve both design efficiency and quality in parallel with shortening time-to-market for customers.

The ASE IDE workflow reduces the overall design cycle time based on two synergistic achievements:

1. Cross platform interaction (layout and verification):
   ASE works with industry-leading EDA tool providers to address software and format compatibility issues that can arise from operating on differing platforms. As a result, layout and verification are both essential yet time-consuming iterative processes within the design workflow. Design complexity can result in thousands of verification errors in the first design layout. Significant effort is required to resolve every error and continues throughout the entire cyclical design & verification phase. ASE has streamlined the compatibility between multiple EDA vendors to simplify the layout and verification process, which has resulted in a 50% cycle time reduction during this phase.