GBT Commenced Design Productivity Software Solutions Development
Part of its 3D Monolithic, Multi-Dimensional/Plane, Memory Structure - Integrated Circuits Allowance Commercialization
SAN DIEGO, Nov. 02, 2020 (GLOBE NEWSWIRE) -- GBT Technologies Inc. (OTC PINK: GTCH) ("GBT”, or the “Company”) announced that GBT together with Alpha EDA (“Alpha”), its joint venture partner, have
developed IC design productivity enhancement algorithms and methods. This technology is aiming to accelerate microchips design process with a focus on advanced nodes of 7nm and below. The IC
industry has been following Moore’s law for many decades which provides that “The number of transistors on a chip becomes double approximately every two years”.
As the demand for semiconductor products and features continues to grow, the industry demands advanced IC design technology in order to be able to provide affordable, smart chips, with low power consumption and high performance. Foundries (the factories that manufacturing the actual chips) are moving toward lower geometries (FinFET 7nm, 5nm and the upcoming 3nm) for fabricating next generation electronics. Designing microchips in lower geometries has become a major challenge. The geometrical/physical design rules of the tiny transistors are becoming a bottleneck when it comes to achieving reasonable chips design time. The physical limitations of the small node silicon device create steep challenges to handle and cause long and expensive IC design time. Another significant aspect is the time to market factor. Projects are taking much longer time due to complex design rules and process related constraints. This fact enforces Electronic Design Automation (“EDA”) vendors to constantly develop new solutions and approaches for the industry’s needs but they are not able to catch up with the advancements of the deep nanometer progress. As processes are moving into 7nm and below, the current physical design/verification tools do not provide sufficient performance.
Consequently, designs do not meet their tape-out schedules and furthermore, fail to meet functionalities and electrical rules. New approaches and methods are needed to address deep nanometer design requirements, in a reasonable time manner.
Alpha has developed new systems and methods to enhance the productivity of ICs design process. In addition, GBT’s existing technology is designed to enhance performance and shorten the scope of physical verification checks to quickly resolve complicated nanometer manufacturing design rules. Chips will become more power efficient, higher performance and more compact, which will have a significant impact on the silicon yield. We conservatively estimate that using Alpha developments with GBT's technologies may save between 40%-50% of an IC design cycle, eliminating design rules automatically and during early stages. These interactive technologies identify design violations during the construction of IC layout and eliminate them in real-time. In addition, Alpha's productivity solutions address electrical rules violations in order to maintain chip's power efficiency, high reliability, and high performance operation.
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