Cadence Accelerates On-Device and Edge AI Performance and Efficiency with New Neo NPU IP and NeuroWeave SDK for Silicon Design - Seite 2

The flexible Neo NPUs are well suited for ultra-power-sensitive devices as well as high-performance systems with a configurable architecture, enabling SoC architects to integrate an optimal AI inferencing solution in a broad range of products, including intelligent sensors, IoT and mobile devices, cameras, hearables/wearables, PCs, AR/VR headsets and advanced driver-assistance systems (ADAS). New hardware and performance enhancements and key features/capabilities include:

• Scalability: Single-core solution is scalable from 8 GOPS to 80 TOPS, with further extension to hundreds of TOPS with multicore
• Broad configuration range: supports 256 to 32K MACs per cycle, allowing SoC architects to optimize their embedded AI solution to meet power, performance and area (PPA) tradeoffs
• Integrated support for a myriad of network topologies and operators: enables efficient offloading of inferencing tasks from any host processor—including DSPs, general-purpose microcontrollers or application processors—significantly improving system performance and power
• Ease of deployment: shortens the time to market to meet rapidly evolving next-generation vision, audio, radar, natural language processing (NLP) and generative AI pipelines
• Flexibility: Support for Int4, Int8, Int16, and FP16 data types across a wide set of operations that form the basis of CNN, RNN and transformer-based networks allows flexibility in neural network performance and accuracy tradeoffs
• High performance and efficiency: Up to 20X higher performance than the first-generation Cadence AI IP, with 2-5X the inferences per second per area (IPS/mm²) and 5-10X the inferences per second per Watt (IPS/W)

Since software is a critical part of any AI solution, Cadence also upgraded its common software toolchain with the introduction of the NeuroWeave SDK. Providing customers with a uniform, scalable and configurable software stack across Tensilica DSPs, controllers and Neo NPUs to address all target applications, the NeuroWeave SDK streamlines product development and enables an easy migration as design requirements evolve. It supports many industry-standard domain-specific ML frameworks, including TensorFlow, ONNX, PyTorch, Caffe2, TensorFlow Lite, MXNet, JAX and others for automated end-to-end code generation; Android Neural Network Compiler; TF Lite Delegates for real-time execution; and TensorFlow Lite Micro for microcontroller-class devices.