Seagate Designs RISC-V Cores to Power Data Mobility and Trustworthiness

Seagate Technology plc (NASDAQ: STX) announced that it has designed two processors based on the open RISC-V instruction set architecture (ISA).

One of the open standards-enabled cores is designed for high performance and the other is area-optimized. The high-performance processor has already been built with RISC-V-enabled silicon and demonstrated as functional in hard disk drives (HDDs). The area-optimized core has been designed and is in the process of being built.

Because both processors offer RISC-V security features, the benefits add up to more robust edge-to-cloud data trustworthiness, security, and mobility—all essential in the era when so much data is on the move.

The announcement, made today at the virtual RISC-V Summit 2020, is the first public report on the results of Seagate’s several years of collaboration with RISC-V International.

“Having shipped close to one billion cores over the last year, Seagate has developed significant expertise in system-on-a-chip design,” said Cecil Macgregor, Vice President, Application-Specific Integrated Circuit (ASIC) Development. “We now expanded the capability to add customized RISC-V cores to our portfolio, which is critical to future products. We live in a time of unprecedented growth of enterprise data—and much of this data is in motion. These cores will allow devices to share a common RISC-V ISA. Using open security architectures, they will enable more secure movement of data.”

The high-performance core offers up to triple the performance for real-time, critical HDD workloads versus current solutions. In an initial use case, this core enabled Seagate to dramatically increase the real-time processing power available. The processor paves the way for finer positioning by implementation of advanced servo (motion control) algorithms.

The area-optimized core boasts a highly configurable microarchitecture and feature set. It’s optimized both for footprint and power savings. It powers auxiliary, supporting, or background workloads. It can execute security-sensitive edge computational operations (including next-generation post-quantum cryptography) while targeting a small-footprint implementation of security features over performance.

One of the key use cases for this core is security. A member of OpenTitan, Seagate is committed to open and transparent security.

“We see a significant potential for open, extensible architectures like RISC-V,” said Dominic Rizzo, OpenTitan Project Director and Engineering Lead at Google Cloud. “OpenTitan’s open-source implementation benefits from RISC-V’s open nature, enabling pan-industry transparency, trust,, and silicon security. Because Seagate understands the promise of RISC-V for security, we are excited to collaborate with Seagate on the open-source silicon root of trust we are currently developing.”