Simplex Solutions(SPLX) - 500 Beiträge pro Seite

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Profile:Simplex Solutions, Inc. provides software and services for integrated circuit design and verification to enable its communications, computer and consumer products customers to achieve production success and rapid delivery of complex systems-on-chip. System-on-chip refers to an integrated circuit that includes computing, memory and communications components previously available only on separate chips. The Company`s customers can gain a competitive advantage by using its products and services in advance of manufacture to design and verify integrated circuits that will perform as intended, taking into account the effects of deep-submicron semiconductor physics. Customers using the Company`s products include AMD, ATI Technologies, Cadence Design Systems, Conexant Systems, Inc., Infineon, Intel Corporation, LSI Logic, Philips Semiconductors, Silicon Graphics, Inc., Sony Corporation, STMicroelectronics, Sun Microsystems, Texas Instruments Incorporated, Toshiba and Vitesse Semiconductor.

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http://www.simplex.com




Deloitte & Touche Name Simplex to Technology `Fast 50` List
Ranking Confirms Simplex as One of Silicon Valley`s Fastest-Growing Technology Companies
SUNNYVALE, Calif., Sept. 11 /PRNewswire/ -- Simplex Solutions, Inc. (Nasdaq: SPLX - news), a leading provider of software and services for the design and verification of integrated circuits, today announced that the company has been named to the prestigious Deloitte & Touche Technology ``Fast 50`` Program for Silicon Valley, a ranking of the 50 fastest-growing technology companies in the area. Rankings are based on companies` percentage growth in revenue during the five-year period from 1996 to 2000.

Penny Herscher, Simplex chairman and CEO, said, ``We are very proud of this recognition. I credit Simplex`s impressive revenue growth over the past five years to our customers` support of our technology, and to our extraordinary people and their commitment to building a world-class company.``

``With its ranking on the Deloitte & Touche Technology Fast 50, Simplex Solutions` leaders have proven that they have the vision and the fortitude to excel in the highly competitive technology industry,`` said Roy Avondet, managing partner of Deloitte & Touche`s Northern California and Hawaii Technology & Communications Group. ``We congratulate Simplex on becoming one of the 50 fastest-growing technology companies in Silicon Valley.``

To qualify for the Fast 50, companies must have had operating revenues of at least $50,000 in 1996 and $1,000,000 in 2000; must be public or private companies headquartered in Silicon Valley; and must be ``technology companies,`` defined as companies that produce technology, manufacture a technology product or devote a high percentage of effort to research and development of technology. Deloitte & Touche will announce the complete list of Technology Fast 50 companies and their rankings on September 20, 2001.

About Simplex

Simplex Solutions, Inc. provides software and services for the design and verification of integrated circuits to enable its communications, computer and consumer-products customers to achieve first-time production success and rapid delivery of complex systems-on-chip. Simplex`s customers use its products and services prior to manufacture to design and verify the integrated circuits to help ensure that the integrated circuits will perform as intended, taking into account the complex effects of deep-submicron semiconductor physics. Simplex can be reached at 408-617-6100 or on the web at www.simplex.com.


Simplex Solutions, Inc.
521 Almanor Ave.
Sunnyvale, Calif. 94086
408-617-6100 tel [phone] fax


NOTE: Simplex Solutions and the Simplex logo are trademarks of Simplex Solutions. All other trademarks mentioned in this press release are the properties of their respective owners.

SOURCE: Simplex Solutions, Inc.

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X Initiative Members Successfully Collaborate on X Architecture Mask Manufacturability
Numerical`s Results Confirm Design-to-Manufacturing Link for Breakthrough X Architecture Chips
SUNNYVALE, Calif., Oct. 8 /PRNewswire/ -- The X Initiative, a semiconductor supply-chain consortium, today announced the results of a successful effort by charter member Numerical Technologies, Inc. (Nasdaq: NMTC - news) to process the first X Architecture photomask data with optical proximity correction (OPC), based on design data provided by charter member Simplex Solutions, Inc. (Nasdaq: SPLX - news). Numerical used its CATS(TM) mask data preparation (MDP) tool -- which is used in virtually every photomask manufacturing facility worldwide to prepare design information for mask manufacturing -- to assess MDP for X Architecture designs, both with and without the addition of OPC. Numerical`s CATS was able to efficiently process the X Architecture geometries, demonstrating comparable results with traditional designs in terms of both processing time and data volume.

Numerical`s results, which confirm that today`s industry-standard MDP tool is well suited for processing X Architecture designs for mask production, bears out the expectation that X Architecture designs will not fundamentally change key fabrication steps. This experiment will help accelerate the adoption of the X Architecture as a production-worthy approach to the pervasive use of diagonal interconnect, which drives a host of benefits, including improved chip performance, power consumption and number of working chips per wafer.

``Based on these results, we are confident that the X Architecture can be processed for mask making through Numerical`s data preparation and OPC solutions,`` said Atul Sharan, Numerical`s senior vice president of marketing and business development. ``With our comprehensive design-to-silicon solution portfolio, Numerical is in a unique position to enable and optimize the link from design-to-manufacturing as new technologies such as the X Architecture are adopted.``

In a separate announcement today*, the X Initiative announced the successful production of the world`s first X Architecture mask by DuPont Photomasks, Inc. DuPont Photomasks was able to produce this first-of-its-kind photomask leveraging today`s mask manufacturing software and equipment, including CATS, for current-generation 0.18-micron process technologies. Using 0.18-micron design data in GDSII format, supplied by Simplex, DuPont Photomasks determined that all test results fall within the range of normal compared to ``Manhattan`` designs using only right-angle interconnects.

Commenting on the significance of these efforts, Aki Fujimura, president and chief operating officer of Simplex Solutions, said, ``Numerical`s experiments have helped to confirm both that X Architecture masks are manufacturable and that the supply chain is in place to deliver cost-effective X Architecture masks to IC manufacturers.``

Facilitating collaborative work to accelerate the readiness of the supply chain is the fundamental mission of the X Initiative. Anyone interested in learning more about the X Initiative or the mask results above is invited to attend the X Initiative Open Forum on October 11 at the Westin Hotel in Santa Clara, Calif., beginning at 12 noon. Speakers will include DuPont`s Ken Rygler; Paul DePesa, director of strategic marketing for Numerical; and Simplex`s Aki Fujimura. Those interested may RSVP or learn about other Open Forum dates and locations at www.xinitiative.org.

About the X Architecture

The X Architecture, the first production-worthy approach to the pervasive use of diagonal interconnect, reduces the total interconnect, or wiring, on a chip by more than 20 percent. Based on initial evaluations, this wire-length reduction is expected to deliver simultaneous improvements of 10+ percent greater chip performance, 20+ percent less power dissipation, and 30+ percent more chips per wafer for complex, multiple-metal-layer ICs such as systems-on-chip (SoCs). For the past 20 years, chip design has been primarily based on the defacto industry standard ``Manhattan`` architecture, named for its right-angle interconnects resembling a city-street grid. The X Architecture rotates the primary direction of the interconnect in the fourth and fifth metal layers by 45 degrees from a Manhattan architecture. The new architecture maintains compatibility with existing cell libraries, memory cells, compilers and IP cores by preserving the Manhattan geometry of metal layers one through three.

About the X Initiative

The X Initiative, a group of leading companies from throughout the semiconductor industry, is chartered with accelerating the availability and fabrication of the X Architecture, a revolutionary interconnect architecture based on the pervasive use of diagonal routing. The X Initiative`s five-year mission is to provide an independent source of education about the X Architecture, to facilitate support and fabrication of the X Architecture through the semiconductor industry supply chain, and to survey usage of the X Architecture to track its adoption. Representing leaders spanning the entire design-to-silicon infrastructure, X Initiative members include: Artisan Components, Inc. (www.artisan.com); Dai Nippon Printing (www.dnp.co.jp); DuPont Photomasks, Inc. (www.photomask.com); Etec Systems, Inc., an Applied Materials, Inc. company (www.etec.com); KLA-Tencor Corporation (www.kla-tencor.com); Matsushita Electric Industrial Co., Ltd. (www.matsushita.co.jp); Numerical Technologies, Inc. (www.numeritech.com); PDF Solutions, Inc. (www.pdf.com); Silicon Perspective Corp. (www.siperspective.com); Simplex Solutions, Inc. (www.simplex.com); STMicroelectronics (www.st.com); Tensilica, Inc. (www.tensilica.com); Toshiba Machine Co., Ltd. (www.toshiba-machine.com); Toshiba Corporation (www.toshiba.com); and Virtual Silicon Technology, Inc. (www.virtual-silicon.com). Membership is open to all companies throughout the semiconductor supply chain; materials can be found at www.xinitiative.org.

Cautionary Note Regarding Forward-looking Statements

This release contains forward-looking statements (including, without limitation, information regarding semiconductor design, production and performance improvements resulting from the X Architecture, the compatibility of the X Architecture with current technology, the future success of X Architecture technology and the ability of certain of the X Initiative members to support the X Architecture) that involve risks and uncertainties that could cause the results of X Initiative members and other events to differ materially from managements` current expectations.

Actual results and events may differ materially due to a number of factors, including, among others: future strategic decisions made by the X Initiative members; failure of the X Architecture to enable the production of designs that are feasible and competitive with current designs or future alternatives; future strategic decisions made by X Initiative members or others that inhibit the development of the X Architecture; demand for advanced semiconductors that are developed using the X Architecture; cost feasibility of the production of semiconductors designed using the X Architecture; and the rapid pace of technological change in the semiconductor industry. The matters discussed in this press release also involve risks and uncertainties described in the most recent filings of the X Initiative members with the Securities and Exchange Commission. The X Initiative members assume no obligation to update the forward-looking information contained in this release.

See ``DuPont Photomasks Successfully Produces the World`s First X Architecture Mask.``
SOURCE: Simplex Solutions, Inc.

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DuPont Photomasks Successfully Produces the World`s First X Architecture Mask
DuPont Photomasks` Results Confirm Manufacturability Using Conventional Equipment
SUNNYVALE, Calif., Oct. 8 /PRNewswire/ -- The X Initiative, a semiconductor supply-chain consortium, today announced the results of a successful effort by charter members DuPont Photomasks, Inc. (Nasdaq: DPMI - news) and Simplex Solutions, Inc. (Nasdaq: SPLX - news) to produce the first X Architecture photomask. DuPont Photomasks used existing photomask production equipment to successfully write and inspect an X Architecture test mask, based on Simplex-generated design data. DuPont Photomasks determined all test results fall within the range of normal as compared to traditional designs.

The rapid success of this early mask experiment has broad implications for the future manufacture of X Architecture chips. First, it bears out the expectation that X Architecture designs will not fundamentally change key fabrication steps. Second, DuPont Photomasks confirmed that advanced laser-based mask pattern generation systems are well suited for writing X Architecture masks. These results will help accelerate the adoption of the X Architecture as a production-worthy approach to the pervasive use of diagonal interconnect, which drives a host of benefits, including improved chip performance, power consumption and number of working chips per wafer.

Of particular significance is the fact that DuPont Photomasks was able to produce this first-of-its-kind photomask, leveraging today`s mask manufacturing software and equipment, for current-generation 0.18-micron process technologies. Using 0.18-micron design data in GDSII format supplied by Simplex and fractured using CATS(TM), an industry-standard photomask data preparation software from Numerical Technologies, DuPont Photomasks was able to write the X Architecture mask utilizing Etec Systems` ALTA 3700 laser mask pattern generation system and inspect it with a KLA-Tencor 363UV inspection system. After inspecting the mask and evaluating the impact on runtimes and data sizes, DuPont Photomasks determined all test results fall within the range of normal compared to ``Manhattan`` designs using only right-angle interconnects.

``Our ability to quickly and cost-effectively produce a test X Architecture photomask using today`s equipment is really a step forward,`` said Ken Rygler, executive vice president of worldwide marketing and strategic planning at DuPont Photomasks. ``We`re pleased to contribute to the X Initiative because it supports our strategic goal to help customers adopt new technologies that improve device performance and reduce their manufacturing costs. We`re delighted to be at the forefront of this exciting initiative.``

Commenting on the significance of these efforts, Aki Fujimura, president and chief operating officer of Simplex Solutions, said, ``This successful X Initiative collaboration with DuPont Photomasks confirms the manufacturability of the X Architecture as the next innovation in semiconductor design. These test results indicate that X Architecture masks are manufacturable and that the supply chain is in place to deliver cost-effective X Architecture masks to IC manufacturers.``

Facilitating collaborative work to accelerate the readiness of the supply chain is the fundamental mission of the X Initiative. Anyone interested in learning more about the X Initiative or the aforementioned mask results is invited to attend the X Initiative Open Forum on Thursday, October 11, at the Westin Hotel in Santa Clara, Calif., beginning at 12 noon. Speakers will include DuPont Photomasks` Rygler, Simplex`s Fujimura and Numerical`s Paul DePesa, director of strategic marketing. Those interested may RSVP or learn about other Open Forum dates and locations at www.xinitiative.org.

About the X Architecture

The X Architecture, the first production-worthy approach to the pervasive use of diagonal interconnect, reduces the total interconnect, or wiring, on a chip by more than 20 percent. Based on initial evaluations, this wire-length reduction is expected to deliver simultaneous improvements of 10+ percent greater chip performance, 20+ percent less power dissipation, and 30+ percent more chips per wafer for complex, multiple-metal-layer ICs such as systems-on-chip (SoCs). For the past 20 years, chip design has been primarily based on the defacto industry standard ``Manhattan`` architecture, named for its right-angle interconnects resembling a city-street grid. The X Architecture rotates the primary direction of the interconnect in the fourth and fifth metal layers by 45 degrees from a Manhattan architecture. The new architecture maintains compatibility with existing cell libraries, memory cells, compilers and IP cores by preserving the Manhattan geometry of metal layers one through three.

About the X Initiative

The X Initiative, a group of leading companies from throughout the semiconductor industry, is chartered with accelerating the availability and fabrication of the X Architecture, a revolutionary interconnect architecture based on the pervasive use of diagonal routing. The X Initiative`s five-year mission is to provide an independent source of education about the X Architecture, to facilitate support and fabrication of the X Architecture through the semiconductor industry supply chain, and to survey usage of the X Architecture to track its adoption. Representing leaders spanning the entire design-to-silicon infrastructure, X Initiative members include: Artisan Components, Inc. (www.artisan.com); Dai Nippon Printing (www.dnp.co.jp); DuPont Photomasks, Inc. (www.photomask.com); Etec Systems, Inc., an Applied Materials, Inc. company (www.etec.com); KLA-Tencor Corporation (www.kla-tencor.com); Matsushita Electric Industrial Co., Ltd. (www.matsushita.co.jp); Numerical Technologies, Inc. (www.numeritech.com); PDF Solutions, Inc. (www.pdf.com); Silicon Perspective Corp. (www.siperspective.com); Simplex Solutions, Inc. (www.simplex.com); STMicroelectronics (www.st.com); Tensilica, Inc. (www.tensilica.com); Toshiba Machine Co., Ltd. (www.toshiba-machine.com); Toshiba Corporation (www.toshiba.com); and Virtual Silicon Technology, Inc. (www.virtual-silicon.com). Membership is open to all companies throughout the semiconductor supply chain; materials can be found at www.xinitiative.org.

Cautionary Note Regarding Forward-looking Statements

This release contains forward-looking statements (including, without limitation, information regarding semiconductor design, production and performance improvements resulting from the X Architecture, the compatibility of the X Architecture with current technology, the future success of X Architecture technology and the ability of certain of the X Initiative members to support the X Architecture) that involve risks and uncertainties that could cause the results of X Initiative members and other events to differ materially from managements` current expectations. Actual results and events may differ materially due to a number of factors, including, among others: future strategic decisions made by the X Initiative members; failure of the X Architecture to enable the production of designs that are feasible and competitive with current designs or future alternatives; future strategic decisions made by X Initiative members or others that inhibit the development of the X Architecture; demand for advanced semiconductors that are developed using the X Architecture; cost feasibility of the production of semiconductors designed using the X Architecture; and the rapid pace of technological change in the semiconductor industry. The matters discussed in this press release also involve risks and uncertainties described in the most recent filings of the X Initiative members with the Securities and Exchange Commission. The X Initiative members assume no obligation to update the forward-looking information contained in this release.

SOURCE: Simplex Solutions, Inc.

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X Initiative Rapidly Builds Momentum as Total Membership Passes 20
Eight New Companies Sign On to Support Consortium`s Charter to Drive Adoption of the X Architecture
SUNNYVALE, Calif., Oct. 8 /PRNewswire/ -- Marking a significant milestone reached in only four months since its inception, the X Initiative today announced that eight companies have joined the semiconductor supply chain consortium, bringing its total membership to 23. The new members join those already signed on in supporting the X Initiative`s charter to facilitate and accelerate the industry`s adoption of the X Architecture. This breakthrough innovation in semiconductor physical design -- the industry`s first major advancement in this area in 15 years -- is also the first to enable chipmakers to realize simultaneous benefits in chip performance, cost and power consumption.

The new X Initiative members comprise suppliers of electronic design products and services, intellectual property (IP), and photomasks. They include: MicroArk Co. Ltd. (Tokyo, Japan); Monterey Design Systems, Inc. (Sunnyvale, Calif.); NurLogic Design, Inc. (San Diego, Calif.); Photronics Inc. (Jupiter, Fla.); Prolific, Inc. (Newark, Calif.); Silicon Logic Engineering, Inc. (Eau Claire, Wis.); SiliconMap, LLC. (Livermore, Calif.); and Virage Logic, Inc. (Fremont, Calif.).

Together with the companies previously committed to participation in the X Initiative, these latest additions give the X Initiative the distinction of having as members the world`s top three suppliers in several important markets, including standard-cell IP and photomasks. ``This momentum validates the potential of the X Architecture. These companies are well-positioned as early adopters to reap the reward of market share as the technology moves into the mainstream,`` said Jan Willis, X Initiative steering group facilitator and vice president of business development at Simplex. ``The Initiative will continue to facilitate early leverage for its members through projects like the recent DuPont Photomasks and Numerical Technologies experiments.``

Dr. Kenji Yoshida, general manager, design technology development department, Semiconductor Technology Academic Research Center (STARC, Tokyo, Japan), agrees that ``first mover advantage`` is a key motivation for companies to join the X Initiative, and believes that the trend of rapid adoption will continue. ``Early supporters will have an advantage in the X Architecture market segment that will dominate the market for complex chips with five or more metal layers in a few years` time,`` said Dr. Yoshida. ``I`m delighted to see this high level of support from the market-leaders in the mask-making and IP supply chain and I hope to see similar progress by leaders in the EDA sector soon.``

On October 11, the X Initiative is sponsoring a free Open Forum educational seminar on the topic of X Architecture photomask creation, open to all those interested in the X Initiative and X Architecture photomask results. The free luncheon seminar will be held from noon to 2 p.m. at the Westin Hotel in Santa Clara, Calif. More details and membership information are available at www.xinitiative.org.

About the X Architecture

The X Architecture, the first production-worthy approach to the pervasive use of diagonal interconnect, reduces the total interconnect, or wiring, on a chip by more than 20 percent. Based on initial evaluations, this wire-length reduction is expected to deliver simultaneous improvements of 10+ percent greater chip performance, 20+ percent less power dissipation, and 30+ percent more chips per wafer for complex, multiple-metal-layer ICs such as systems-on-chip (SoCs). For the past 20 years, chip design has been primarily based on the defacto industry standard ``Manhattan`` architecture, named for its right-angle interconnects resembling a city-street grid. The X Architecture rotates the primary direction of the interconnect in the fourth and fifth metal layers by 45 degrees from a Manhattan architecture. The new architecture maintains compatibility with existing cell libraries, memory cells, compilers and IP cores, by preserving the Manhattan geometry of metal layers one through three.

About the X Initiative

The X Initiative, a group of leading companies from throughout the semiconductor industry, is chartered with accelerating the availability and fabrication of the X Architecture, a revolutionary interconnect architecture based on the pervasive use of diagonal routing. The X Initiative`s five-year mission is to provide an independent source of education about the X Architecture, to facilitate support and fabrication of the X Architecture through the semiconductor industry supply chain, and to survey usage of the X Architecture to track its adoption. Representing leaders spanning the entire design-to-silicon infrastructure, X Initiative members include: Artisan Components, Inc. (www.artisan.com); Dai Nippon Printing (www.dnp.co.jp); DuPont Photomasks, Inc. (www.photomask.com); Etec Systems, Inc., an Applied Materials, Inc. company (www.etec.com); KLA-Tencor Corporation (www.kla-tencor.com); Matsushita Electric Industrial Co., Ltd. (www.matsushita.co.jp); MicroArk Co. Ltd. (www.microark.co.jp); Monterey Design Systems, Inc. (www.montereydesign.com); Numerical Technologies, Inc. (www.numeritech.com); NurLogic Design, Inc. (www.nurlogic.com); PDF Solutions, Inc. (www.pdf.com); Photronics Inc. (www.phototronics.com); Prolific Inc. (www.prolificinc.com); Silicon Logic Engineering, Inc. (www.siliconlogic.com); SiliconMap, LLC. (www.siliconmap.net); Silicon Perspective Corp. (www.siperspective.com); Simplex Solutions, Inc. (www.simplex.com); STMicroelectronics (www.st.com); Tensilica, Inc. (www.tensilica.com); Toshiba Machine Co., Ltd. (www.toshiba-machine.com); Toshiba Corporation (www.toshiba.com); Virage Logic, Inc. (www.viragelogic.com); and Virtual Silicon Technology, Inc. (www.virtual-silicon.com). Membership is open to all companies throughout the semiconductor supply chain; materials can be found at www.xinitiative.org.

Cautionary Note Regarding Forward-looking Statements

This release contains forward-looking statements (including, without limitation, information regarding semiconductor design, production and performance improvements resulting from the X Architecture, the compatibility of the X Architecture with current technology, the future success of X Architecture technology and the ability of certain of the X Initiative members` to support the X Architecture) that involve risks and uncertainties that could cause the results of X Initiative members and other events to differ materially from managements` current expectations.

Actual results and events may differ materially due to a number of factors including, among others: future strategic decisions made by the X Initiative members; failure of the X Architecture to enable the production of designs that are feasible and competitive with current designs or future alternatives; future strategic decisions made by X Initiative members or others that inhibit the development of the X Architecture; demand for advanced semiconductors that are developed using the X Architecture; cost feasibility of the production of semiconductors designed using the X Architecture; and the rapid pace of technological change in the semiconductor industry. The matters discussed in this press release also involve risks and uncertainties described in the most recent filings of the X Initiative members with the Securities and Exchange Commission. The X Initiative members assume no obligation to update the forward-looking information contained in this release.

New X Initiative Member Quotes

``We see the X Architecture as a significant step in physical design. We are pleased to join the X Initiative because we believe the X Architecture addresses the needs of our customers` complex SoC designs,`` stated Dr.Hiroshi Murata, president of MicroArk Co.,Ltd. (Tokyo, Japan). ``We believe that the X Architecture is compatible with our Sequence-Pair based physical design technology, we expect it to become a leading a new design solution for our customers.``

``The goals of the X Initiative are well aligned with our focus on high-bandwidth connectivity solutions for the rapidly growing communications infrastructure markets, as well as with our baseline IP business model,`` said Darla Berkel, senior product marketing manager for NurLogic Design, Inc. (San Diego, Calif.). ``The X Architecture offers improvements of greater chip performance and less power dissipation, which are much needed in the communications infrastructure space. The compatibility with existing cell libraries and IP cores will be a benefit to our IP customers.``

``The practical application of diagonal interconnect has been a bit of a Holy Grail in IC design, so we are gratified to see the X Initiative`s promise to place this technology in the hands of designers,`` said Paul de Dood, President and CEO of Prolific, Inc. (Newark, Calif.). ``Furthermore, we see vital synergy in combining methodologies. Prolific improves area, power, and performance for standard-cells, the building blocks of ICs, by creating optimized Liquid Cells(TM) on the fly. With the X Architecture driving the same enhancements at the interconnect level, customers can combine our approaches to leapfrog several barriers to successful design.``

``Most new designs have over 50 % of the area consumed by embedded memory. As the largest supplier of these memories, Virage Logic is focused on providing high density memories to meet our customer needs,`` said Vincent Ratford, vice president of marketing at Virage Logic (Fremont, Calif.). ``We`re pleased to support the X Initiative so that customers can achieve higher densities on the rest of their chip and reduce their overall costs.``

``The benefits of the X Architecture are as dazzling as the technical challenges are daunting. A widespread collaborative effort comprising expertise in all areas of design, implementation, and manufacturing is needed to reap those benefits,`` stated Jacques Benkoski, president and CEO of Monterey Design Systems (Sunnyvale, Calif.). ``As the only provider of a complete system-driven physical design solution, we believe that we have much to contribute. We look forward to working together with the elite members of this initiative for the benefit of our customers.``

``SLE is proud to be a part of the X Initiative. SLE is known for its ability to design very large, high-speed ASICs, and adoption of the X Architecture will mean we can push our customers` designs to new levels of complexity and performance,`` said Mike Berry, chief technology officer of Silicon Logic Engineering (Eau Claire, Wis.).

``The X Architecture will allow SoC designers to achieve the same power and density advantages at the chip level that SiliconMap`s designers have implemented in full custom physical designs in the past,`` stated Pallab Chatterjee, president and CTO of SiliconMap, LLC (Livermore, Calif). ``The decision to join the X Initiative was to expand the multi-vendor design flow development and optimization services for the SoC customer base. We feel that this architecture will be prevalent in the majority of future designs and the development of a seamless integration path for these tools into traditional DSM flows without additional schedule impacts is goal of SiliconMap, LLC and it`s Integration Alliance Partners.``

``Photronics is committed to supporting innovations that improve semiconductor performance, increase functionality, and reduce die costs per wafer, which in turn have been the source of explosive semiconductor industry growth. The X Architecture holds the promise to be just such an innovation,`` commented Steve Carlson, senior vice president, technology of Photronics, Inc. (Jupiter, Fla.). ``Photronics` proprietary Sub-Wavelength Reticle Solutions technology will facilitate the quick and cost-effective integration of the X Architecture into high-performance semiconductor designs seeking to fully leverage its capability.``

SOURCE: Simplex Solutions, Inc.

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Simplex Solutions Reports Financial Results for Fourth Quarter and Fiscal 2001
Company Posts Tenth Consecutive Quarter of Record Revenue
SUNNYVALE, Calif., Oct. 23 /PRNewswire/ -- Simplex Solutions, Inc. (Nasdaq: SPLX - news) today reported its fourth quarter and fiscal year results for the period ended September 30, 2001. For the fourth quarter of fiscal 2001, Simplex reported revenue of $14.3 million and pro forma net income of $982,000, or $0.06 per share. Pro forma net income excludes stock-based compensation expense and amortization of acquired intangible assets. This compares to revenue of $7.3 million and pro forma net income of $318,000, or $0.04 per share, for the fourth quarter of fiscal 2000.

For the 12-month period ended September 30, 2001, Simplex reported revenue of $48.2 million and pro forma net income of $1,783,000, or $0.13 per share. This compares to revenue of $22.8 million and pro forma net income of $648,000, or $0.08 per share, for the 12-month period ended September 30, 2000.

Financial results prepared in accordance with generally accepted accounting principles (GAAP) are shown below.

``I`m pleased with our fourth-quarter and fiscal year-end results, particularly in light of a difficult global economic environment,`` commented Penny Herscher, chairman and CEO of Simplex Solutions, Inc. ``Annual revenue grew 111 percent, and we increased pro forma net income by 175 percent. I am also pleased with our ability to serve our customers with leading-edge products and services as they move to 0.13-micron technology. Additionally, we made significant technological progress on the X Architecture while strengthening our X Initiative semiconductor supply-chain partnerships.``

Simplex will hold a conference call that includes a business outlook, with financial analysts and investors today at 2:00 p.m. PDT. A live webcast of the call will be available from www.StreetFusion.com and through a link on the Simplex website at www.simplex.com. Those wishing to listen to the telephone replay may call 719-457-0820, access code 480092, beginning at 5:00 p.m. PDT today and ending on October 31, 2001. A webcast replay will also be available from www.StreetFusion.com and through a link on the Simplex site at www.simplex.com from approximately 5:00 p.m. PDT today and ending on October 31, 2001.

Cautionary Note Regarding Forward-looking Statements

This release contains forward-looking statements (including, without limitation, the adoption of 0.13 micron technologies and Simplex`s ability to continue to serve its customers with leading-edge products and services for these technologies) that involve risks and uncertainties that could cause the results of Simplex to differ materially from management`s current expectations.

Actual results may differ materially due to a number of factors including, among others: future strategic decisions made by Simplex; competitive developments; cost feasibility of 0.13-micron technology; demand for advanced semiconductor chips; and the rapid pace of technological change in the semiconductor industry. The matters discussed in this press release also involve risks and uncertainties described in Simplex`s most recent filings with the Securities and Exchange Commission. Simplex assumes no obligation to update the forward-looking information contained in this release.

About Simplex

Simplex Solutions, Inc. provides software and services for the design and verification of integrated circuits (ICs) to enable its communications, computer and consumer-products customers to achieve first-time production success and rapid delivery of complex systems-on-chip. Simplex`s customers use its products and services prior to manufacture to design and verify ICs and help ensure they will perform as intended, taking into account the complex effects of deep-submicron semiconductor physics. Simplex can be reached at 408-617-6100 or on the web at www.simplex.com.


Simplex Solutions, Inc.
Pro Forma Condensed Consolidated Statements of Operations (A)
(in thousands, except per share data)
(Unaudited)

Three Months Twelve Months
Ended Ended
Sept. 30, Sept. 30, Sept. 30, Sept. 30,
2001 2000 2001 2000

Revenue:
Software-license $7,132 $4,350 $24,722 $14,679
Software-service 2,947 2,923 10,622 8,138
Design foundry 4,225 -- 12,840 --
Total revenue 14,304 7,273 48,184 22,817

Costs of Revenue:
Cost of software 43 18 70 92
Cost of service 732 1,124 3,051 3,391
Cost of design 2,079 -- 6,820 --
Total cost of
revenue 2,854 1,142 9,941 3,483

Gross Margin 11,450 6,131 38,243 19,334

Expenses:
Selling and
marketing 5,157 3,346 17,832 10,373
Research and
development 3,640 1,509 12,597 4,966
General and
administrative 1,629 760 5,449 2,821
Total
operating
expenses 10,426 5,615 35,878 18,160

Income from
operations 1,024 516 2,365 1,174

Interest and
other income 448 38 849 178
Interest
expense (6) (109) (341) (462)

Income before
income taxes 1,466 445 2,873 890

Provision for
income taxes 484 127 1,090 242

Net income $982 $318 $1,783 $648

Basic net
income
per share $0.07 $0.09 $0.19 $0.23

Diluted
pro forma
net income
per share $0.06 $0.04 $0.13 $0.08

Shares used in
calculation
of basic
net income
per share 14,651 3,412 9,311 2,802
Shares used in
calculation
of diluted
pro forma
net income
per share 16,975 8,944 13,833 8,061



(A) Pro forma net income excludes the impact of amortization of acquired intangibles, stock-based compensation and in-process research and development.
Simplex Solutions, Inc.
Condensed Consolidated Statements of Operations
(in thousands, except per share data)
(Unaudited)

Three Months Twelve Months
Ended Ended
Sept. 30, Sept. 30, Sept. 30, Sept. 30,
2001 2000 2001 2000

Revenue:
Software-license $7,132 $4,350 $24,722 $14,679
Software-service 2,947 2,923 10,622 8,138
Design foundry 4,225 -- 12,840 --
Total revenue 14,304 7,273 48,184 22,817

Costs of Revenue:
Cost of software 43 18 70 92
Cost of service 732 1,124 3,051 3,391
Cost of design 2,079 -- 6,820 --
Total cost
of revenue 2,854 1,142 9,941 3,483

Gross Margin 11,450 6,131 38,243 19,334

Expenses:
Selling and
marketing 5,157 3,346 17,832 10,373
Research and
development 3,640 1,509 12,597 4,966
General and
administrative 1,629 760 5,449 2,821
Amortization
of acquired
intangibles 1,646 289 6,570 575
Stock-based
compensation 1,797 539 7,300 1,795
In-process
research and
development -- -- -- 5,000
Total
operating
expenses 13,869 6,443 49,748 25,530

Loss from
operations (2,419) (312) (11,505) (6,196)

Interest and
other income 448 38 849 178
Interest
expense (6) (109) (341) (462)

Loss before
income taxes (1,977) (383) (10,997) (6,480)

Provision for
income taxes 484 127 1,090 242

Net loss $(2,461) $(510) $(12,087) $(6,722)

Basic net
loss per
share $(0.17) $(0.15) $(1.30) $(2.40)

Shares used in
calculation
of basic
net loss
per share 14,651 3,412 9,311 2,802


Simplex Solutions, Inc.
Condensed Consolidated Balance Sheet
(in thousands)

Sept. 30, Sept. 30,
2001 2000 (A)
(Unaudited)

Cash, cash equivalents and
short-term investments $50,671 $7,447
Accounts receivable, net 17,237 7,142
Prepaid expenses and other
current assets 1,588 356
Total current assets 69,496 14,945

Property and equipment, net 5,114 1,742
Other assets 458 891
Intangible assets, net 24,379 4,938

Total assets $99,447 $22,516

Line of credit, net of discount $-- $2,442
Accounts payable 1,859 741
Accrued liabilities 7,792 3,439
Deferred revenue 7,781 5,654
Total current liabilities 17,432 12,276

Other long term liabilities
and notes payable 272 321
Total liabilities 17,704 12,597

Convertible preferred stock -- 24,251

Total stockholders` equity
(deficit) 81,743 (14,332)

Total liabilities and
stockholders`equity $99,447 $22,516


(A) Derived from audited financial statements as of September 30, 2000.

SOURCE: Simplex Solutions, Inc.

[panik]

Simplex Awarded Two Patents for IC Noise Modeling
Substrate Noise Technology Helps Ensure First-Silicon Success For Advanced RF and Wireless Chips
SUNNYVALE, Calif., Nov. 12 /PRNewswire/ -- Simplex Solutions, Inc. (Nasdaq: SPLX - news), a leading provider of software and services for the design and verification of integrated circuits (ICs), today announced it has been awarded two U.S. patents for its innovative methods of modeling noise in IC substrates. The technologies defined in these patents -- along with several other proprietary, advanced modeling techniques -- are integrated within Simplex`s SubstrateStorm(TM) substrate noise analysis tool, the industry`s most accurate substrate noise modeling product.

Substrate noise is a key issue for designers of today`s complex deep-submicron systems-on-chip, particularly for those designing sensitive, high-speed chips for radio-frequency (RF) and wireless applications, noted Penny Herscher, Simplex chairman and CEO. ``Simplex`s mission is to supply our customers with the critical design and verification solutions they need to achieve first-silicon success,`` said Herscher. ``Protecting our investment in our technology is vital to the success of that mission. These patents speak to the technical excellence of our research and development team, and their ability to deliver advanced, differentiated solutions to our customers.``

Substrate noise is created when unintended electrical effects generated by the digital transistors on a chip are transmitted through the base material, or substrate, of the chip to other parts of the circuit, affecting the performance of those features. Substrate noise modeling technologies simulate the causes and effects of substrate noise in an IC so that chip designers can better protect the performance of sensitive elements of their chips. SubstrateStorm is the most accurate substrate noise analysis technology available because it incorporates the highly detailed modeling techniques described in the two newly awarded patents.

The first of the two patents, U.S. No. 6,291,322, describes the master framework for the substrate noise modeling methodology, which includes building a detailed model of the complex layers that comprise a chip`s substrate, then defining the vertical column of the substrate that lies directly beneath each of the chip`s transistors. This unique, highly detailed modeling methodology is built into SubstrateStorm, and provides users with the most accurate possible analysis. Patent inventor Francois Clement, Ph.D., director of the Substrate/Mixed-Signal team at Simplex, said, ``Accuracy is absolutely paramount for designers of sensitive RF or wireless circuits, where even very slight variations in signal fidelity can mean the difference between function and failure.``

The second of the two patents, U.S. No. 6,291,324, invented by a Simplex team led by senior engineer Jerome Lescot, describes a refinement of the methodology to include yet more detailed information on the composition of the substrate. This addition, the result of extensive and on-going research and development by Simplex`s Substrate/Mixed-Signal team, further enhances the accuracy of the analysis provided by SubstrateStorm, ensuring that the technology keeps pace with the rapidly evolving demands of the fast-paced wireless/RF marketplace.

About Simplex

Simplex Solutions, Inc. provides software and services for the design and verification of integrated circuits to enable its communications, computer and consumer-products customers to achieve first-time production success and rapid delivery of complex systems-on-chip. Simplex`s customers use its products and services prior to manufacture to design and verify the integrated circuits to help ensure that the integrated circuits will perform as intended, taking into account the complex effects of deep-submicron semiconductor physics. Simplex can be reached at 408-617-6100 or on the web at www.simplex.com

NOTE: Simplex Solutions, the Simplex logo, and SubstrateStorm are trademarks of Simplex Solutions. All other trademarks mentioned in this press release are the properties of their respective owners.

SOURCE: Simplex Solutions, Inc.

[panik]

IDT Adopts Simplex`s VoltageStorm SoC
Leading Communications IC Provider Says Power Grid Verification Essential in 0.13-Micron Design Flow
SUNNYVALE, Calif., Nov. 26 /PRNewswire/ -- Simplex Solutions, Inc. (Nasdaq: SPLX - news), a leading provider of software and services for the design and verification of integrated circuits (ICs), today announced that leading communications integrated circuit provider IDT (Nasdaq: IDTI - news) has adopted Simplex`s VoltageStorm(TM) SoC power grid verification software as a standard part of IDT`s next-generation design flow for its value-added communications ICs. IDT will use VoltageStorm SoC -- the leading power grid verification solution -- to verify the impact of deep-submicron effects -- such as power grid IR (voltage) drop and electromigration risk, on IDT`s advanced semiconductor products targeted at communications infrastructure applications.

``Power grid verification is an essential step for designs targeted at and below 0.13 micron,`` said Anwar Hasan, director of design automation at IDT. ``We selected Simplex`s VoltageStorm SoC because of the accuracy of the embedded transistor-level engine fueling the tool`s fast, hierarchical power grid analysis and verification. With VoltageStorm SoC as part of our next-generation design flow, we`re confident that we will be able to understand and account for the impact of voltage drop on our designs before tapeout.``

Until the advent of deep-submicron process technologies, IR drop was considered a second- or third-order effect. Today`s high-performance SoC designs, with their increasing chip size and number of integrated IP blocks, as well as decreasing power supply voltages, are at increased risk for IR drop-related failures due to the unpredictable flow of power in and around embedded blocks. At 0.13 micron, IR drop has become a signal integrity issue, and can have direct impact on a chip`s timing. Accordingly, SoC designers require verification tools with an embedded transistor-level engine for accuracy combined with automated, hierarchical model generation to rapidly provide a solution to the timing, power and signal-integrity issues of 0.13-micron design.

``Leading-edge companies, like IDT, understand that at ultra-deep-submicron technologies, IR drop is a first-order effect that can have broad-ranging impact on a chip`s timing and reliability,`` said Jim Bailey, general manager of Simplex`s SoC verification business. ``We are very pleased to be able to provide IDT with a solution to this critical problem, helping them to achieve first-silicon success for their advanced process technology designs.``

About IDT

IDT enhances the global network with semiconductor solutions for communications companies that lead innovation and drive convergence in voice, data and wireless networks. Communications-industry leaders choose IDT for its high-performance products that accelerate time to market and boost bandwidth in the network infrastructure. IDT`s communications-specific products include integrated processors, IP co-processors and telecom products; its foundational product portfolio is comprised of the industry`s broadest selection of FIFOs, multi-ports, and clock management products; and the company`s product mix also incorporates high-performance digital logic and SRAMs to meet the requirements of communications systems.

Headquartered in Santa Clara, Calif., the company employs approximately 3,800 people worldwide and has manufacturing facilities in California, Oregon, the Philippines and Malaysia. IDT stock is traded on the Nasdaq stock market under the symbol ``IDTI.`` Additional information about IDT is easily accessible at www.idt.com or on CD-ROM by calling 800-345-7015. The investor hotline is 408-654-6420.

About Simplex

Simplex Solutions, Inc. provides software and services for the design and verification of integrated circuits to enable its communications, computer and consumer-products customers to achieve first-time production success and rapid delivery of complex systems-on-chip. Simplex`s customers use its products and services prior to manufacture to design and verify the integrated circuits to help ensure that the integrated circuits will perform as intended, taking into account the complex effects of deep-submicron semiconductor physics. Simplex can be reached at 408-617-6100 or on the web at www.simplex.com.

Cautionary Note Regarding Forward-Looking Statements

This release contains forward-looking statements (including, without limitation, information regarding IDT benefiting from the use of VoltageStorm SoC and its use ensuring first-silicon success) that involve risks and uncertainties that could cause the results of Simplex to differ materially from management`s current expectations.

Actual results may differ materially due to a number of factors including, among others: future strategic decisions made by Simplex and/or IDT; competitive developments; demand for advanced semiconductor chips and the verification software that supports their production; and the rapid pace of technological change in the semiconductor industry. The matters discussed in this press release also involve risks and uncertainties described in Simplex`s most recent filings with the Securities and Exchange Commission. Simplex assumes no obligation to update the forward-looking information contained in this release.

NOTE: Simplex Solutions, the Simplex logo, and VoltageStorm are trademarks of Simplex Solutions. All other trademarks mentioned in this press release are the properties of their respective owners.

SOURCE: Simplex Solutions, Inc.

[panik]

[Chipdesign]

hi

Wie ich bemerke ist simplex noch unbekannt in deutschland?

Das wird sich ändern,es ist ein perle!!!!

ich werde mal einige beiträge übersetzt posten!

Die X-Architektur Die x-Architektur ist eine neue Verknüpfung Architektur, die auf dem durchdringenden Gebrauch von diagonaler Wegewahl basiert. Gezielt an den Chips mit dreht fünf oder mehr Metallschichten, die x-Architektur die Primärrichtung der Verknüpfung in den 4. und 5. Metallschichten durch 45 Grad in bezug auf herkömmliches orthogonales oder " ein Manhattan, " Architektur. Schichten eine bis drei bleiben unverändert und konservieren die Investition des Designs community.s in vorhandenen Zellenbibliotheken, die Speicherzellen, die Speichercompiler, die datapathcompiler und die harten Kerne IP. Zusätzlich erlaubt die x-Architektur 45-Grad- " Falschweise Stöße, ", die zusätzlichen vier Freiheitsgrade in jeder Schicht von Wegewahl liefert.


Der durchdringende Gebrauch X Architecture.s von diagonaler Wegewahl verringert Leitung-Länge durch einen Durchschnitt 20%, und das resultiert in den simultanen Verbesserungen in der Chip-Geschwindigkeit, -energie und -kosten. Gegründet auf Design bis jetzt, resultiert x-Architekturchips werden erwartet zu haben: 10+% verbesserte Leistung 20+% niedriger schalten Ableitung 30+% mehr Arbeitschips pro Oblate an, die die ganze dieser Nutzen zu einer erhöhten Wahrscheinlichkeit des Erstsilikonerfolges beitragen. Zusätzlich bildet die Verkleinerung Leitung-Länge X Architecture.s das Wegewahlproblem 20% einfacher zu lösen, und das resultiert im schnelleren Zeitbegrenzungschliessen, in verbesserter Zuverlässigkeit und in einer Verringerung der Signal-Vollständigkeit Probleme.



Simplexbetrieb aktiviert die x-Architektur Diagonale Wegewahl, mit seinen mehr direkter Anschluß der Chip-Bestandteile, ist nicht eine neue Idee. Voll-Gewohnheit und Speicherdesigns haben Hand-verlegte Diagonalen für die kurzen, lokalen Wege für Jahre benutzt. Und das Konzept einer Architektur mit den 4. und 5. Metallschichten, die durch 45 Grad gedreht werden, ist in den akademischen Kreisen für fast als lang behandelt worden und debattiert worden. Jedoch ist erfolgreiche Implementierung der Architektur, bis heutigen Tag, schwer bestimmbar gewesen, weil das automatische körperliche Design und parasitschen die Extraktion- und Analysentechnologien, die, um durchdringende diagonale Wegewahl automatisch zu erstellen angefordert wurden und zu formen, nicht existierenten. Über drei Jahren vor, erkannte Simplexbetrieb diese Gelegenheit für Innovation, und Set über den komplizierten und intensiven Prozeß der Erfindung der Entwurfstechnologien, die Chip-Hersteller aktivieren würden, Nutzen aus dem Nutzen leicht zu ziehen, bot durch den durchdringenden Gebrauch von diagonaler Verknüpfung an. Simplexbetrieb hat mit Toshiba Corporation für mehr als zwei Jahre auf der Möglichkeit und der Entwicklung der x-Architektur zusammengearbeitet.


Flüssige WegewahlTechnologie Simplex.s Gerade da über-d-Zelle Wegewahl die Meer-von-Gatterarchitektur in den achtziger Jahren aktivierte, wird die x-Architektur durch Simplex.serfindung einer neuen Wegewahltechnologie aktiviert: flüssige Wegewahl, die erste Anwendung des gridless, octilinear Bereiches, der auf Chip-Entwurf verlegt. Diese radikal unterschiedliche Annäherung zum Abbrechen von Wegewahl -- wenn die Verknüpfung durch ein Rasterfeld nicht begrenzt ist und, sich in irgendwelche von acht Richtungen zu bewegen fähig -- ist was die durchdringende diagonale Wegewahl X Architecture.s aktiviert und Resultate in den Leitung-Länge Verkleinerungen, die die Leistung, die Energie und den Sterben zerkleinernnutzen der Architektur antreiben.

Durchdringende Innovation Erfolgreiche Implementierung der x-Architektur benötigt buchstäblich Dutzende Innovationen in der körperlichen Design- und Überprüfungstechnologie. Gleichmäßig über den offensichtlichen Änderungen an den wireloadmodellen und an den Verzögerung Schätzungtechnologien, Änderungen hinaus werden auch in den zusätzlichen Bereichen wie Dateiaustauschformaten und in den graphischen Anzeigesystemen angefordert. Zusätzlich zur flüssigen Wegewahltechnologie hat Simplexbetrieb die parasitsche Extraktiontechnologie entwickelt, die zur Formung des Widerstandes und der Kapazitanz der durchdringenden diagonalen Leitungen fähig ist. Und, zwecks das Maximum zu ernten profitiert von der Wegewahl X Architecture.s, Simplexbetrieb hat entwickelt Bestückungstechnik, die durchdringende diagonale Wegewahl vorwegnimmt.

KollektivZusammenarbeit Immer wenn es eine Haupthalbleiterprozess- oder -artinnovation gibt, wird Mitarbeit während der Zubehörkette angefordert, um manufacturability und ökonomische Entwicklungsfähigkeit sicherzustellen. Die größten Interessen beziehen im Allgemeinen die Auswirkung auf Ergebnis, Photomaske Produktion und Kosten, die Verwendbarkeit der angeforderten Design- und Überprüfungshilfsmittel, sowie das Management der Datenanforderungen und des Datendatenträgers durch die Zubehörkette mit ein. um diese Interessen für die x-Architektur zu adressieren, hat eine wachsende Gruppe führende Firmen während von der Halbleiterzubehörkette die x-Initiative gebildet: eine Vereinigung, damit Zubehörkette Versorger über die x-Architektur, beschleunigen Herstellung der x-Architekturchips erlernen und Erfolg durch erstes Silikon und jenseits aufspüren und fördern. Simplexbetrieb ist stolz, Toshiba als zu verbinden Co-fördern von der x-Initiative. Zu mehr Information über die x-Architektur und die x-Initiative, besuchen Sie das x-Initiative website an http://www.xinitiative.org.

Der Pfad zu X Toshiba, als der Ausgangslizenznehmer der Simplextechnologien, die die x-Architektur aktivieren, produziert die ersten x-Architekturchips. Simplexbetrieb setzt seine aktivierende Technologie ein, um eine begrenzte Anzahl von x-Architekturchips für Kunden dieses Jahr zu erstellen. X sind Architekturchips im Allgemeinen vorhanden, beide durch die SimplexSoC-Designgießerei und durch genehmigende Vorbereitungen mit Halbleiterpartnern, zur Hälfte zweite von 2002.






diese aktie wird der highflyer!!!!!

[Chipdesign]

und weiter geht es......



SoC-Designgießerei in einer Industrie, in der Marktwindows shrinking gleichmäßiges schnelleres als abbrechen Technologien sind, ein sachverständiges Designanlieferung Team zum Sicherstellen Sie habend sind Erst-zumarkt ist die Taste zum Erfolg. Dieses ist, wo die SimplexSoC-Designgießerei helfen kann. Das SoC-Design-Gießereiteam kombiniert eine schnelle, scalable Methodenlehre mit in hohem Grade leverageable Entwurfstechnologie und elektrischer Sachkenntnis DSM, um Ihren SoC-DesignErst-zumarkt und -datenträger zu liefern. Das SoC-Design-Gießereiteam hat einen nachgewiesenen Spursatz, wenn es Anforderungen des Systems und die elektrischen des Designs SoC adressiert und komplette Designkreation vom abschließenden netlist zum tapeout innerhalb vier bis sechs Wochen bereitstellt. Ihre Schaltungsentwurfsachkenntnis umfaßt analoges Design, wie PLLs und Voll kundenspezifischen Entwurf, wie DLLs, Taktrückgewinnungstromkreise, Taktgebersynthesizer, Quarzoszillatoren und eingebettete Speicher. Wenn Sie Komplex, Multi-Milliongatter, tief-deep-submicron SoCs entwerfen, kann integrierte Methodenlehre der SoC-Design-Gießerei für first-pass elektrisches Schliessen Ihnen helfen, elektrische Designpunkte wie anzusprechen:

analoge Integration Netzverteilung und das Entkoppeln des Schaltung Geräuschmanagements (einschließlich Reflexionen und Übersprechen) unsere SoC-Designmethodenlehre wird weiter mittels Extraktionhilfsmittel, -feuer u. -eis QX und -VoltageStorm SoC DSM 3d des Simplexbetriebs erfinderisches für Vollchip-Energie Rasterfeldanalyse erhöht. Es sind auch einer der zwei Premiereversorger der erfinderischen neuen x-Architektur. SoC-Designgießerei hat Technologie, um high-volume Ergebnis mit erstem Silikon sicherzustellen entwickelt und anwendet und eine schnelle Rampe-oben zur Massenproduktion so aktiviert.

Führen Sie SoC-Überprüfung Durch Hauptströmungsdesign hat sich auf Verfahrenstechniken des Vor-Viertelmikrons und Designarten des System-auf-Chips (SoC) bewogen, die mehrfache Stufen von Logik und von Funktionalität auf einem einzelnen Chip enthalten. um tief-deep-submicron (DSM) SoC-Designs zu überprüfen, benötigen Sie multi-level Extraktion- und Analysenhilfsmittel, die Auswirkung der DSM-Effekte, wie IR Tropfen- und Substratgeräusche, auf Leistung Ihrer Chips, Energie Vollständigkeit, Substratvollständigkeit, Signalvollständigkeit und reliability.all auszuwerten, von denen Auswirkung Zeit-zu-Markt und Ergebnis und Chip-Ausfall verursachen können. So vor kurzem fünf Jahre vor, hatte Einheitparasitics die größte Auswirkung auf Leistung und Vollständigkeit Ihres wie Designs. Mit der Bewegung zu den DSM-Prozessen, wurde Verknüpfung parasitics eine Primärüberprüfung Ausgabe. Als das Laufen lassen der Frequenzen und der Dichten Ihrer Designs fahren Sie fort, sich zu erhöhen, Sie muß das parasitics verstehen, das mit dem IS-Substrat dazugehörig ist. Eine komplette SoC-Überprüfung Lösung muß Extraktion umfassen und Analyse nicht nur von schält und Einheiten, aber des zugrundeliegenden Substrates außerdem zusammen.


SUBSTRATESTORM-Substrat-Geräuschformung und Analyse, die formen u. Analyse genaues Substrat, das interaktive Sichtbarmachungintegration mit Normalausfühhrung Flussprodukthöhepunkten formt Das in hohem Grade genaue Substrat 3d, das schneller 100X, 10X mehr Kapazität als vorhergehende Versionen formt, unterstützt hochentwickelten CMOS, BiCMOS, SiGe, und reine zweipolige Verfahrenstechniken mit leicht lackiertem, Epitaxial- oder SOI-AUTOMATISCHEM, anpassungsfähigem Oberflächenrasterfeldmassenerzeugung für Genauigkeit und Leistungsfähigkeit graphische Sichtbarmachung der eigenen PerturbingPathTM Technologie der Oberflächengeräuschverteilung kennzeichnet die bedienungsfreundliche graphische Benutzerschnittstelle der Geräuschpfade, die mit Normalausfühhrung Flüssen integriert wird: GDSII, CIF gaben GEWÜRZ, HSPICE, Eldo und ERSCHEINUNG-Ausgabeschnittstellen mit analogem ArtistTM- und VirtuosoTM-Klima des Rhythmus ein



SubstrateStorm: Formung U. Analyse Die kleineren Eigenschaft Größen, die höheren Dichten, die höheren Frequenzen und niedrigeren die Zubehörspannungen der heutigen komplizierten tiefen submicron Designs des System-auf-Chips (DSM) (SoC) haben die Substrat-Geräusche gebildet, die eine Schlüsselausgabe für Entwerfer verbinden. Alle Design gerichteten Verfahrenstechniken des Vor-Viertelmikrons können zum Substratparasitics verletzbar sein. Zum Beispiel wenn Sie Mischensignalstromkreise entwerfen, müssen Sie über digitale Geräuschkoppelung in empfindlichen analogen Schaltkreis betroffen werden. Wenn Sie ein Entwerfer der Hochfrequenz (HF) sind, sorgen sich Sie um Geräusche von der Mischerkoppelung in den lärmarmen Verstärker (LNA). auch, Ihre hohe Geschwindigkeit digitalen Designs sind noise Koppelung in Phase-Verriegelung Schleifen (PLLs) und die Erhöhung des Bammels verletzbar. Bis jetzt sind Sie erzwungen worden, Richtlinie-von-Daumenmethodenlehren zu verwenden, um gegen das Substratübersprechen zu schützen und geschätzt, wie man weit Schutzringe bildet und wo man Zubehör anschließt. Häufig sind diese Richtlinie-von-Daumenkorrekturlinien unzulängliche oder Erzeugnisdesigns, die über-ausgeführt werden. In jedem Fall können Sie nicht, nah Ihr Design zum Ausfall ist. SubstrateStorm bietet eine formale Methodenlehre an, die Sie mit zuverlässigen quantitativen Resultaten versieht, indem es genau das Substrat der großen Chips formt, die in jeder neuen Technologie fabriziert werden. Sie können experimentieren, indem Sie zusätzliche Schutzringe hinzufügen und die Netzverteilung ändern, oder, die Plazierung der lauten oder empfindlichen Blöcke ändernd, bestimmen Sie dann die Übertragungsgüte jeder Lösung mit SubstrateStorm mengenmäßig. SubstrateStorm kann verwendet werden, um eine genaue Ansicht der Geräuschkoppelung über Ihrem Substrat zu erhalten, während Sie Zellen und Blöcke, während des Floorplannings und während des Layouts entwerfen.


SubstrateStorm: In hohem Grade genaues Substratformen, 100X, ob Sie, versuchen die Auswirkung der Geräusche vom digitalen Teil Ihres Mischensignals SoC auf Ihre Geräusch-empfindlichen analogen Blöcke zu verstehen, oder ein hochentwickeltes Design Bluetooth, Genauigkeit formend schneller erstellen ist Ihre ersten Kriterien für ein Substratanalyse Hilfsmittel. Mit hochentwickeltem Halbleiter-Physikwissen und ausführlichen Technologiekennzeichnungprofilen gibt SubstrateStorm Ihnen die genaueste vorhandene Substratformung - ein Minimum Genauigkeit 80% über einer breiten Strecke der Technologien einschließlich CMOS, BiCMOS, SiGe und der reinen zweipoligen Prozesse auf leicht den lackierten, Epitaxial- oder SOI-Oblaten. um ein Substratmodell zu produzieren, legt SubstrateStorm automatisch ein Ineinandergreifen 3d, mit vertikalen Gitterlinien fest, die Ihre Prozeßdotierungsprofile und ein Oberflächenrasterfeld, das von Ihrem Layout berechnet wird passen. Das Oberflächenrasterfeld wird aus den mit hoher Schreibdichteregionen konstruiert, die durch das grobe Ineinandergreifen getrennt werden und leistungsfähig fokussiert Genauigkeit in den Bereichen des größten Interesses. Ein Set justierenparameter stellt ausser Kraft setzt zur Verfügung, die Sie aktivieren, das automatische Erzeugung des Oberflächenrasterfeldes zu steuern. Jetzt mit SubstrateStorm 3,1, können Sie dieses in hohem Grade genaue Substrat erhalten, das schneller 100mal als mit vorhergehenden Versionen formt. Diese Geschwindigkeit, verbunden mit Genauigkeit, aktiviert Sie, schnell zu verstehen, wie Blockplazierung und -abhängigkeit Ihr Design beeinflussen, wie Sie Ihr floorplan erstellen. SubstrateStorm 3,1 kennzeichnet auch eine Verbesserung der Kapazität 10X. Da Sie Zellen und Blöcke entwerfen, können Sie SubstrateStorm 3,1 verwenden, um ein ausführliches Modell jeder möglicher Struktur zu produzieren, die bis 50.000 Substratzugriff Kanäle enthält (empfindliche oder laute Einheiten, Substrat- oder Vertiefungsgleichheit) und erstellen Ineinandergreifen mit Dichten bis bis 10 Million Knotenpunkten 3d und zu eine Million Oberflächenknotenpunkten. Mit dieser Arbeitsfähigkeit an der Zelle, am Block und an den Vollchip-Stufen, während aller Stadien des körperlichen Designs, wird SubstrateStorm eindeutig entsprochen, um die Herausforderungen des SoC-Designs und -überprüfung zu treffen. SubstrateStorm produziert die GEWÜRZNETLISTS, die für die allgemeinsten elektrischen Simulatoren verwendbar sind. Eigenschaft des SubstrateStorm`s-Eigentümers NetConnect(tm) bezieht automatisch Substratmodelle mit Ihren ursprünglichen Stromkreisnetzen aufeinander, und effortlessly backannotates, die das Substratsubcircuit durch SubstrateStorm in das ursprüngliche Stromkreisnetlist festlegte.


Sind schnelle, genaue Technologie-Kennzeichnungprofile der Technologie Kennzeichnung genau geschilderte die Grundlage für die genaue Substratformung. SubstrateStorm`s-Technologie-Kennzeichnunghilfsmittel kann Modelle für die hochentwickeltesten Silikonprozesse, einschließlich der komplizierten Strukturen wie dreifache Vertiefungen, die begrabenen Schichten, Mehrfachverbindungsstelle die wohlen Tiefen, die Gräben und die seitlichen Substratkoppelung Effekte wie Seitenwände der Vertiefungen und die widerstrebenden Effekte innerhalb der Vertiefungen erstellen. Mit eingebauter Halbleiter-Physiksachkenntnis SubstrateStorm`s optimale Substratkennzeichnungen von den Prozeßinformationen ist zu erstellen schnell und einfach. Wenn Sie fabless sind, versehen einige Halbleiterproduktionsgesellschaften verschlüsselte Prozeßmodelle für Gebrauch mit SubstrateStorm. SubstrateStorm: Interaktive Sichtbarmachung Easy-to-Use Bedienungsfreundliche Schnittstelle SubstrateStorm`s und VollcFarbe Sichtbarmachung versehen Sie mit einem leistungsfähigen Hilfsmittel für das Analysieren des Substratübersprechens, und Lösungen interaktiv erforschen zu den Geräuschproblemen. Während des Zelle Designs aktiviert eigene PerturbingPath Technologie SubstrateStorm`s Sie, den Koppelung Pfad zwischen den lauten und empfindlichen Bereichen zu finden. Während des Floorplannings während Sie mit verschiedenen Blockplazierungen experimentieren, können Sie SubstrateStorm`s-Extraktion und -simulation verwenden, um zu verstehen, wie die Plazierung der lauten Logik empfindliche analoge Blöcke beeinflußt, und die optimale Lokalisierung Lösung zu kennzeichnen. Während des Layouts zeigt SubstrateStorm`s-Sichtbarmachung der Geräuschverteilung offenbar topologische Ausgaben sowie Schutzdefekte an. SubstrateStorm: Integration mit Normalausfühhrung Flüssen Durch den Gebrauch von industriekompatiblen Austauschformaten, schließt SubstrateStorm direkt an Designhilfsmittel von den meisten Haupt-cEda-Firmen, einschließlich des Rhythmus DIVATM und DRACULATM an. SubstrateStorm unterstützt auch GDS-II, CIF- und GEWÜRZ-Formate. SubstrateStorm`s-Projektorschnittstelle ist als SubstrateStormCDS, eine Steckverbindung zum Layoutherausgeber der Rhythmuskonstruktionssysteme vorhanden.




Störende Pfadfähigkeit Hilfen kennzeichnen Sie topologische Ausgaben sowie Geräusch-Schutzmängel




DEEP-SUBMICRONCAnalyse HILFSMITTEL Report ElectronStorm ClockStorm SI zusätzlich zu VoltageStorm. SoC, Simplexbetrieb bietet einen Suite Transistor-Stufe der tief-deep-submicron Analyse Produkte an. Diese Hilfsmittel liefern die umfangreichsten Vollchip-Analyse Fähigkeiten, die für Taktgeberschieflaufen, Electromigration und Signal-Vollständigkeit Analysen vorhanden sind. Mit Simplexbetrieb können Sie möglicherweise tödliche Probleme sehen, bevor Sie heraus auf Band aufnehmen. DSM-Analyse Produkte des Simplexbetriebs verwenden die parasitschen Daten, die durch Fire u. Eis QX, Vollchip des Simplexbetriebs, parasitscher Auszieher 3D-accurate extrahiert werden. Feuer u. Eis QX und VoltageStorm SoC Liek, diese Analyse Produkte ist in ihrer Kapazität, in Genauigkeit und in Geschwindigkeit -- außen abhängig von Datenverdichtung unvergleichlich. Alle DSM-Analyse Produkt-Angebot-Standardtextreports des Simplexbetriebs und Produkt einfach-zu-deuten, VollcFarbe graphische Reports, um Ihnen zu helfen, Ihr Chip sichtbar zu machen. ElectronStorm die filterntechnologie des eindeutigen Signals für Electromigration (SIFT-EM) in ElectronStorm. wendet Electromigrationgefahr Analysen an den Taktgeber- und Signaladern und an den vias an. SIFT-EM filtert das Vollchip-netlist, um Segmente oder vias der Signal- oder Taktgebernetze zu kennzeichnen, die gegen Signalelectromigration empfindlilch sein können. ElectronStorm führt dann eine ausführliche Electromigrationanalyse mit Black.s-Gleichung durch, auf jedem Segment oder über gekennzeichnet während des Entstörung Prozesses.


ClockStorm ClockStorm. ist eine automatisierte Pfosten-Layouttaktgeber-Analyse Lösung, die genauen Transistor kombiniert und Verknüpfung Simulation mit graphische Resultate einfach-zu-deuten. ClockStorm enthält einen eindeutigen Vollchip-Taktgeberpfad-Abfragung Algorithmus, der automatisch Ihr komplettes Taktgebernetz vom parasitics ermittelt, das von Fire u. Eis QX und das Transistornetlist extrahiert wird. Wenn es in Verbindung mit VoltageStorm verwendet wird, bietet Simplexenergie Rasterfeld-Analyse Produkt, ClockStorm auch eine eindeutige Fähigkeit für das Enthalten des IR Tropfens des Energie Rasterfeldes in Taktgeberüberprüfung an. Si berichten Simplex.s-Signal-Vollständigkeit über die filterntechnologie (SIEBEN Sie) an, enthalten im SI-Report, wenden Signal-Vollständigkeit Kriterien -- Koppelung Kapazitanz, Laufwerkstärke der Opfer- und Angreifernetze und Eingabe -- an allen Netze in Ihrem Design und bringen eine gefilterte Liste " Signal-Vollständigkeit der kritischen " Netze zurück. Sie können diese gefilterte Liste dann benutzen, um weitere ausführliche Signal-Vollständigkeit Analyse anzutreiben. Si berichten, der die genauen Koppelung Daten benötigt, die durch Fire u. Eis QX produziert werden, ist vorhanden als Option für irgendwelche der Simplexanalyse Hilfsmittel.


Integration der FEUER- u. EISCQx Full-Chip 3d Extraktiontechnologien Gate-Level Transistor-Level in Normalausfühhrung fließt

ProduktHöhepunkte Schnell, benötigt Extraktion 3D-accurate für alle SoC-Überprüfung: Zeitbegrenzung, Energie, Signalvollständigkeit und Zuverlässigkeit. Die der zweiten Generation anpassungsfähige analytische ExtractionTM Formung 3d, die verteilt wurde oder, lumped, verband oder entkoppelte gesprungenes Genauigkeit RC Daten innerhalb / - 10% der Silikongenauigkeit validiert im Silikon, indem sie unbegrenzte Extraktion Gatter-Stufe Kapazität der Gießereien für körperliches Design und Überprüfung führte: Qic EngineTM: mehr als 100X schneller als Auszieher des Vorhergehenderzeugung 3d Single CPU-Vollchip-Extraktion für Gebrauch mit Platz u. verlegen Push-button Benutzerfreundlichkeit: DEF zu DSPF/SPEF mit Extraktionmodi eines des einziger Befehl Schwarz-Kastens und Graukastens integrierte mit Normalausfühhrung Flüssen: DEF/LEF und DEF/GDSII gaben vom Rhythmus, Avant! ein, anderer Platz u. Weg bearbeitet RCDB, das zur Rasterfeldüberprüfung DSPF und SPEF Energie VoltageStormTM SoC des Simplexbetriebs ausgegeben wird zu Synopsys PrimeTimeTM, PearlTM des Rhythmus, andere Zeitbegrenzunganalyse Hilfsmittel ausgegeben wird DSPF/SPEF/RCDB, die ausgegeben werden, um Vollständigkeit Hilfsmitteln von der mehrfachen VerkäuferTransistor-stufe Extraktion für abschließende tapeoutüberprüfung zu signalisieren: Nachgewiesenes multiple-CPU, das verarbeitet, um multi-milliontransistor leistungsfähig zu extrahieren, entwirft Schwarz-Kasten, Graukasten, und fließt die hierarchischen Extraktionfähigkeiten der Weißkastenextraktionmodi, die mit Normalausfühhrung integriert werden, der GDSII-, LEF-/DEF und DEF-/GDSIIINPUT RCDB, der zu den SoC-Überprüfung Hilfsmitteln des Simplexbetriebs ausgegeben wird: VoltageStorm SoC, ElectronStormTM, ClockStormTM, SI-Report DSPF, SPEF, RSPF, GEWÜRZ gab zu Synopsys PathMillTM, GEWÜRZ, Rhythmus SpectreTM, hierarchischer Stromkreissimulator NASSDA HSIMTM und andere Zeitbegrenzunganalyse Hilfsmittel DSPF/SPEF/RCDB, die ausgegeben wurden, um Vollständigkeit Hilfsmitteln von den mehreren Verkäufern zu signalisieren aus

Feuer U. Eis Qx: Die Technologien zwei eigene Technologien -- die QIC-Maschine und anpassungsfähige analytische formende Extraktion 3d -- aktivieren Feuer u. Eis QX, beispiellose Extraktiongeschwindigkeit, 10% gesprungene Genauigkeit und die unbegrenzte Kapazität zu liefern. Geschwindigkeit, Genauigkeit und Kapazität -- keine Kompromisse. QuantenGeschwindigkeit: QIC-Maschine des QIC-Maschine Simplexbetriebs ist die aktivierende Technologie für eine vereinheitlichte Extraktionarchitektur, die Gatter-Stufe Zeitbegrenzungüberprüfung und abschließende tapeoutüberprüfung unterstützt. Die QIC-Maschine ist ein Quantendurchbruch bei der IS-Geometrieverarbeitung. Diese Technologie, aktuell in der Gatter-Stufe Option zum Feuer u. zum Eis QX, setzt Hochleistungsdatenstrukturen und leistungsfähigere Suchalgorithmen ein, damit Berechnungen 3d Extraktiongeschwindigkeiten mehr als 100X schneller als Vorhergehenderzeugung Extraktionhilfsmittel verwirklichen. Einige eindeutige Attribute unterscheiden die QIC-Maschine von anderen Geometrie-geometry-processing Technologien. Entwarf spezifisch, Multi-Milliongatter, Vollchip-Extraktionen zu aktivieren auf einer einzelnen CPU, die QIC-Maschine hat einen extrem kleinen Speicherabdruck, der in die unbegrenzte Kapazität übersetzt. Die Maschine verfeinert fortwährend seine Kernalgorithmen als sie verarbeitet die geometries jedes Designs, " effektiv erlernend ", wie man das Design leistungsfähiger extrahiert, während sie durchführt. Möglicherweise am eindeutigsten, haben die der QIC-Extraktionabläufe Maschine ein lineares Verhältnis zur Designgröße. Silicon-ValidatedGenauigkeit: Enthält anpassungsfähiges analytisches Feuer der Extraktion 3d u. Eis QX auch eine erhöhte Version der Produktion-erwiesenen anpassungsfähigen analytischen Extraktion 3d des Simplexbetriebs, die Technologie formt, die verteilte und verbundene RC-Extraktion mit Feld-Wandlergenauigkeit schneller als überhaupt vorher aktiviert. Ein Suite der analytischen Modelle wird einmal pro Prozeß hergestellt. Während der Extraktion als die QIC-Maschine analysiert geometrisch jeden Leiter in allen drei Maßen, es festlegt die Parameter, die auf sehr spezifischen Regionen 3d basieren, führt dann Parameter zu den analytischen Modellen für Kapazitanzberechnung. Die Modelle setzen eine spezielle Einflussregion ein, bekannt als ein " dynamischer Halo. ", Der Halo berechnet alle kapazitiven Effekte des Nahkörpers und der multi-level Verknüpfung einschließlich der Auswirkung der Kreuzfranse, der Ecken und des kapazitiven Schattierens. Koppelung Kapazitanzspiele eine dominierende Rolle, wenn sie die Leistung der tief-deep-submicron Designs (DSM), also feststellen, anpassungsfähige analytische Formung 3d extrahiert lumped und verteilten völlig Netz-zu-Netz verbundene Kapazitanz. Im Gegensatz zu weniger genauen - 2d, 2D 2d oder " Quasi3d " - Methoden kennzeichnet die anpassungsfähige analytische Formung der Extraktion 3d in drei Maßen alle zusammenwirkenden Nachrichten innerhalb des Kontextes des Leiters, der ausgewertet wird. Weil anpassungsfähige analytische Modelle der Extraktion 3d nicht auf Musterzusammenbringentechniken beruhen, leiden sie nicht unter Grenzwertfehlern. Kann anpassungsfähige analytische Modellskala der Extraktion 3d mit shrinking Prozessen und zunehmenden Designgrößen und über einem ausgedehnten Spektrum der Designarten benutzt werden - ohne für jedes Design " zu justieren ". Gießereipartner des Simplexbetriebs haben die Genauigkeit der anpassungsfähigen analytischen Extraktion 3d des Simplexbetriebs im tatsächlichen Silikon validiert, also können Sie Vertrauen haben, daß Sie Ihre Zeitbegrenzungetats treffen und Ziele entwerfen. Durch die Simplexgießereipartner Programm, werden die Modelle des Simplexbetriebs, genannt IceCapsTM, für sechs der führenden Gießereien der Welt vor-validiert: Gemieteter Halbleiter, IBM, NEC, Toshiba, TSMC und UMC. Diese Modelle sind von den Gießereiwebsites oder direkt vom Simplexbetrieb vorhanden. Sie können Ihre eigenen Modelle für jede Verfahrenstechnik Fähigkeit mit automatisierte IceCaps auch aufbauen Erzeugung des Feuers u. des Eises QX`s völlig, die Prozeßübergänge schnell und einfach bildet.


Feuer U. Eis Qx: Gate-Level Extraktion 3d für Platz- u. Wegzeitbegrenzungüberprüfung Feuer- u. EiscQx Gatter-Stufe Option ist das erste Hilfsmittel der Extraktion 3d für Gebrauch während des Ortes u. des Weges der komplizierten ASIC-/ASSP und System-auf-Chip-(SoC) Designs. Feuer- u. EiscQx Gatter-Stufe Option ist nicht nur mehr als 100X schneller als Auszieher des Vorhergehenderzeugung 3d -- es ist sogar schneller als weniger-genaue 2d Auszieher -- also können Sie Extraktion 3d während des körperlichen Designs schließlich einsetzen. Full-Chipextraktion auf einer einzelnen CPU-Feuer- u. -eiscQx Gatter-Stufe Option enthält die QIC-Maschine Technologie, die völlig verteilte RC-Datenabzüge für Multi-Milliongatter aktiviert, Voll chip-Entwürfe auf einer einzelnen CPU. Dieser Durchbruch beschleunigt Zeitbegrenzungschliessen, indem er jedem körperlichen Konstrukteur Zugriff zu einem Hilfsmittel der Extraktion 3d während des Platzes u. des Weges gibt. Feuer- u. EiscQx Gatter-Stufe Option faßt großes, Dateien des Vollchips DSPF leistungsfähig an und aktiviert Vollchip-Extraktion auf einzelnem, 32-bit PCUs. Push-Button leicht anwendbare Feuer- u. EiscQx Gatter-Stufe Option kennzeichnet einen neuen, radikal streamlined Fluß, der Extraktion einen push-button Prozeß buchstäblich bildet. Alle Extraktionoperationen, vom DEF-NETLISTINPUT, durch Connectivityextraktion, Kapazitanz- und Widerstandsextraktion und RC-Verkleinerung, zur DSPF-/SPEFNETLISTAUSGABE, werden mit einem einzigen Befehl durchgeführt. Zusammen mit einem vereinfachten Installation Prozeß gibt einschrittige Ausführung des Feuers u. des Eises QX Ihnen den schnellen Rücklauf und die Benutzerfreundlichkeit, die Sie für Ihre Designflüsse der Gatter-Stufe ASIC benötigen. Feuer U. Eis Qx: Transistor-Level Extraktion 3d für Full-Chipzeitbegrenzung und Zuverlässigkeit Zeitbegrenzungüberprüfung Feuer- u. EiscQx Transistor-Stufe Option ist das erste Hilfsmittel der Extraktion 3d für Gebrauch in der Vollchip-Transistor-Stufe Zeitbegrenzung und in der Zuverlässigkeit Überprüfung der Gewohnheit, DER ASIC-/ASSP und SoC-Designs. Feuer- u. EiscQx Transistor-Stufe Option kombiniert die Kapazität, Genauigkeit, und Geschwindigkeit, Vollchip-Überprüfung zu aktivieren. Extraktion 3D-Accurate für alle SoC-Überprüfung benötigt Feuer u. ist Option Transistor-Stufe des Eises QX das einzige parasitsche Extraktionprodukt, das über Nacht zur Verfügung stellt, Vollchip, 3D-accurate, Transistor-Stufe Extraktion für abschließende tapeoutüberprüfung. Feuer- u. EiscQx Transistor-Stufe Option Support lumped oder verteilten sich, verbanden oder entkoppelten, Vollchip oder wählten Netto-cRc-Extraktion für Integration mit Zeitbegrenzungvollständigkeit, Signalvollständigkeit, Energie Vollständigkeit und Zuverlässigkeit Lösungen aus. Sie wird seamlessly mit den populärsten Design- und Überprüfungsklimas integriert und stellt den Standard De-facto für Modelle 3D-accurate RC bereit. Mehrprozessorbetrieb für Abfertigungszeitfeuer- u. -eiscQx Transistor-Stufe Option Scalable setzt aktuell multiple-CPU ein, das verarbeitet, um Multi-Milliontransistorchips leistungsfähig zu extrahieren. Er verteilt die Extraktionaufgabe in mehrfache unabhängige Aufgaben, die in der Ähnlichkeit über einem Netz der desktop Maschinen durchgeführt werden können. Feuer U. Eis Qx: Integration in Normalausfühhrung fließt Feuer u. fließt Sitze des Eises QX leicht in Ihre vorhandene körperliche Überprüfung. Sie schließt LEF-/DEF und GDSII-Leser für einfache Integration mit Rhythmus, Avant mit ein! und andere körperliche Designhilfsmittel. Feuer- u. EiscQx Gatter-Stufe Option produziert DSPF oder SPEF, die zu den Zeitbegrenzunganalyse Hilfsmitteln wie Synopsys PrimeTime und Perle des Rhythmus (Abbildung 3) ausgegeben werden. Zusätzlich produziert Feuer- u. EiscQx Transistor-Stufe Option auch RSPF- und GEWÜRZ-Ausgabe, und Simplexbetrieb arbeitet nah mit EDA-Partnern wie Rhythmus, Magma, Mentorgraphiken, Monterey, Nassda, Silikonperspektive, und Synopsys zum Geben der Unterstützung für allgemeines Design fließt.

[Chipdesign]

analytische Extraktion 3D-Adaptive Der Halo berechnet alle kapazitiven Effekte des Nahkörpers und der multi-level Verknüpfung einschließlich der Auswirkung der Kreuzfranse, der Ecken und des kapazitiven Schattierens.





VOLTAGESTORM Soc führen SoC-Energie Rasterfeldüberprüfung Technologiemethodenlehren durch, die Integration mit Normalausfühhrung fließt



ProduktHöhepunkte Die führende Energie Rasterfeld-Überprüfung Lösung, Produktion-geprüft auf Hunderten Designs schalten nur Rasterfeldvollständigkeit Lösung an, die zu irgendeinem Zeitpunkt Rasterfeldüberprüfung Energie des körperlichen Designs der kompletten SoC benutzt werden kann: Hohe Geschwindigkeit, des hierarchischen Rasterfeldes Energie DEF-based EnergienrasterfeldansichtunterstützungsSystem-auf-chip-(SoC) IPWIEDERVERWENDUNGSMETHODENLEHRENVoll-chip-Transistor-Stufenenergien-Rasterfeldsign-off (PGS) statische des Tropfens und des Electromigration IR (Spannung) (EM) Analyse Vor-gekennzeichnete und dynamische Transistorkapazität Transistor-Stufe Genauigkeit Analyse Multi-million mit Gatter-Stufe Geschwindigkeit und Benutzerfreundlichkeit: Eindeutige Transistor-genaue ausführliche Technologie der Energie Rasterfeld-Ansichten AccuraTM für vektor-wenigeraktuelle Verteilung Analyse mit der gut-als-statischen Technologie der Genauigkeit QIC EngineTM, die Überprüfung der Multi-Milliongatterdesigns in der Ansichtstützanalyse Minute" Floorplan " des demontierte Blöcke vereinfachten pass-/failreports basiert auf spezifiziertem IR Tropfenschwellwert aktiviert, verstehen das Verhalten des aktuellen Flussacrossyourchips mit interaktiver Analyse der graphischen Sichtbarmachung mit PGS ExplorationTM für schnelle, EinpassagenECOs


VoltageStorm SoC: Die neue Übersicht der Technologien A Produktion der tief submicron (DSM) Designs, die mit VoltageStorm SoC analysiert wurden, deckte auf, daß 75% der Designs Energie Rasterfeldprobleme hatte, Layoutkorrekturen vor tapeout zu benötigen; 20% hatte tödliche Probleme. Alle diese Designs waren saubere DRC/LVS. Wenn Sie Chips entwerfen, die an > 100 MHZ laufen, haben Sie mehr als drei Schichten Metall, oder Ziel verarbeitet an, oder unterhalb 0,35 µm, müssen Sie sich um die Effekte des IR Tropfens sorgen -- und Sie benötigen ein Hilfsmittel, das Sie aktiviert, jene Effekte zu sehen, bevor Sie heraus auf Band aufnehmen. Hunderte der führenden Designteams haben erlernt, auf VoltageStorm SoC, die Standard-cPgs zu zählen Lösung des Simplexbetriebs de Facto für Vollchip-Überprüfung. Heutiges SoC entwirft (mit ihrer zunehmenden Chip-Größe und Zahl der integrierten IPBLÖCKE und ihren abnehmenden Spg.Versorgungsteilspannungen (seien Sie an erhöhter Gefahr für die IR Tropfen-in Verbindung stehenden Ausfälle wegen des unvorhersehbaren Flusses der Energie in und um und zwischen eingebetteten Blöcken. VoltageStorm SoC ist das erste Transistor-genaue Energie Rasterfeld-Analyse Produkt, das genug für Gebrauch während des körperlichen Designs schnell ist und Zeitbegrenzungüberprüfung von SoC entwirft. Diese Durchbruchtechnologie aktiviert Sie, Tropfenanalyse des Simplexbetriebs früh anzuwenden Produktion-erwiesene IR und vermeidet teures abwärts gerichtetes ECOs, um Energie Rasterfeldprobleme zu beheben. Indem Sie VoltageStorm SoC verwenden, um die Vollständigkeit Ihres Energie Rasterfeldes vor Signalwegewahl zu überprüfen, können Sie unnötiges overdesign beseitigen, Flexibilität für Signalwegewahl gewinnen, und Ihre Zeitbegrenzungschliessenbelastung erleichtern. Energie Rasterfeldanalyse während jedes möglichen Stadiums des körperlichen Designs können Sie VoltageStorm SoC zu irgendeinem Zeitpunkt Ihres körperlichen Design- und Überprüfungsprozesses verwenden, von der Zelle und von der Blockbauweise zum Floorplanning zur Pfosten-Plazierung zum abschließenden sign-off Energie Rasterfeld. VoltageStorm SoC gibt Ihnen die Flexibilität, mit den Blöcken Ihres Designs auf verschiedenen Stufen der Abstraktion zu arbeiten. Während Ihre Designdarstellungen weniger abstrakt werden, wird Ihre Energie Rasterfeldanalyse auch ausführlicher und genau. Zum Beispiel wenn Ihr Design kundenspezifische Zellen oder harte IPBLÖCKE umfaßt, wünschen Sie das Energie Rasterfeld dieser Elemente auf der Transistorstufe vor Ihnen analysieren instantiate sie in Ihrem Design. Anziehende Zelle und Blockenstufe gibt früh in einer hierarchischen Methodenlehre sichert enorme Zeit und Bemühung heraus. Überprüfung wird auch auf der Vollchip-Stufe angefordert, weil Blöcke des Designs auf einander einwirken, wenn sie im vollen Chip zusammengebaut werden. Hier auch, können Fähigkeiten VoltageStorm SoC`s unschaetzbar sein. Während des Floorplannings können Sie floorplan " Ansichten VoltageStorm SoC`s verwenden ", um eine Ausgangsschätzung des Netzverteilung Verhaltens Ihrer verschiedenen Blöcke zur Verfügung zu stellen und ihr schält zusammen - vor Ihnen führen Sie sie ein. Diese Mock-upansichten aktivieren Sie, die Implementierung Ihres Energie Rasterfeldes zu formen, um eine Schätzung von zu erhalten zum Beispiel wieviele Energie Brücken Sie für jeden Block benötigen. Indem Sie gegenwärtig VoltageStorm SoC verwenden, können Sie eine schnelle, frühe Ansicht der globalen Energie Rasterfeldvollständigkeit erhalten und grobe Fehler abfangen und Sie leistungsfähiger aktivieren Energie-Plan. Sie erhalten das wertvollste Feedback, wenn Sie VoltageStorm SoC an Ihrer DesignPfosten-plazierung anwenden, aber vor Signalwegewahl. An dieser Phase können Sie eine genaue und sehr ausführliche Ansicht der abschließenden Netzverteilung Ihres Blockes oder Chips erhalten und überprüfen auf overdesign. Ausführliche Netzverteilung Analyse in diesem Stadium des körperlichen Designs kann Sie aktivieren, hinunter Ihr Energie Rasterfeld zu verdünnen und Ihnen mehr Raum für Signalwegewahl geben. Bevor Sie Ihre ausführliche Wegewahl beenden, können Sie die Fall-instance-based IR Tropfendaten von VoltageStorm SoC während ein Input zu Ihrer Verzögerung Berechnung und zu Zeitbegrenzunggültigkeitserklärung verwenden -- eine lebenswichtige Hinzufügung, als IR Tropfen hat eine bedeutende Auswirkung auf Signalankunft Zeit und Taktgeberschieflaufen. Schließlich sobald Ihr Layout komplett ist, können Sie VoltageStorm SoC verwenden, um eine Endrunde, Vollchip, Transistor-Stufe Überprüfung zu tun. Diese Fähigkeit ist besonders wichtig, wenn Sie kundenspezifische Layoutänderungen am Ende Ihres Designs bilden. VoltageStorm SoC umfaßt die Produktion-erwiesene Transistor-Stufe, Vollchip PGS, daß Simplexkunden haben verwendet

Transistor-Levelgenauigkeit, die der Strom, der Ihr Energie Rasterfeld durchfließt, nicht an den Kanälen der Zellen und DER IPBLÖCKE -- keine stoppt, Ihre Energie Rasterfeldanalyse wenn. Viele Gatter-Stufe Netzverteilung Analyse Hilfsmittel beruhen auf oversimplifications, wie Schwarzverpacken eingebetteten IPBLÖCKEN oder Verwenden der einfachen Energie-Verbrauch Verteilung Modelle und handeln Genauigkeit für Geschwindigkeit. Demgegenüber basiert Analyse VoltageStorm SoC`s auf vor-gekennzeichnetem, Transistor-genauem Energie Rasterfeld " ansieht " von den Zellen eines Designs, von den Blöcken und VON DEN IPELEMENTEN. Vor-gekennzeichnete Bibliothekelemente erleichtern auch die Wiederverwendung Strategien, die zu den SoC-Designarten zentral sind. VoltageStorm SoC enthält eigene Technologie Accura des Simplexbetriebs, die automatisch mehrfache Taktgebergebiete in Ihrem Design analysiert, Gatter und Speicher erkennt, und legt eine gut-als-statische Ansicht Ihrer aktuellen Verteilung -- ohne Vektoren fest. Gate-Levelgeschwindigkeit und Ease-of-Use VoltageStorm SoC enthält eigene QIC-Maschine des Simplexbetriebs Geometrie-geometry-processing Technologie. Diese Technologie setzt Hochleistungsdatenstrukturen und leistungsfähige Suchalgorithmen ein, die Transistor-Stufe Genauigkeit mit Gatter-Stufe Geschwindigkeit und Benutzerfreundlichkeit aktivieren. Erforschung der PGS-Erforschung PGS ist interaktive Fähigkeit Analyse VoltageStorm SoC`s. Sie aktiviert Sie, die Auswirkung der vorgeschlagenen Änderungen an Ihrem Layout schnell festzusetzen, damit Sie ausgewählte Änderungen in einem einzelnen ECO-Durchlauf anstatt das Wiederholen durch die körperliche Designschleife enthalten können. Im PGS-Erforschungmodus können Sie globale Änderungen wie Gradeinteilung aller Metalldrähte oder lokale Änderungen wie Hinzufügen oder Löschen einer einzelnen Leitung vornehmen. Sie können vias und Energie Anschlußstifte auch hinzufügen oder löschen und schreiben einen Änderung Report aus. Zusätzlich zum Finden der Energie Rasterfeld-Vollständigkeit Ausgaben, können Sie PGS-Erforschung auch verwenden, um einen Energie Rasterfeldplan vor Signalwegewahl zu validieren. Sie können auf verschiedenen Energie Rasterfeld-Designoptionen innerhalb des Klimas VoltageStorm SoC erforschen und einen einzelnen Änderung Report dann ausschreiben, der das optimale Energie Rasterfelddesign reflektiert. Indem Sie diese Eigenschaft früh in der Designphase verwenden, können Sie Ihren Signalwegewahlbereich maximieren. Der Strom, der Ihr Energie Rasterfeld durchfließt, stoppt nicht an den Kanälen der Zellen und DER IPBLÖCKE -- keine, Ihre Energie Rasterfeldanalyse wenn. Viele Gatter-Stufe Netzverteilung Analyse Hilfsmittel beruhen auf oversimplifications, wie Schwarzverpacken eingebetteten IPBLÖCKEN oder Verwenden der einfachen Energie-Verbrauch Verteilung Modelle und handeln Genauigkeit für Geschwindigkeit. Demgegenüber basiert Analyse VoltageStorm SoC`s auf vor-gekennzeichnetem, Transistor-genauem Energie Rasterfeld " ansieht " von den Zellen eines Designs, von den Blöcken und VON DEN IPELEMENTEN. Vor-gekennzeichnete Bibliothekelemente erleichtern auch die Wiederverwendung Strategien, die zu den SoC-Designarten zentral sind. VoltageStorm SoC enthält eigene Technologie Accura des Simplexbetriebs, die automatisch mehrfache Taktgebergebiete in Ihrem Design analysiert, Gatter und Speicher erkennt, und legt eine gut-als-statische Ansicht Ihrer aktuellen Verteilung -- ohne Vektoren fest. VoltageStorm SoC: Die Methodenlehren Mehrfache Transistor-Stufe PGS der Energie Rasterfeldanalyse Methodenlehren VoltageStorm SoC`s aktiviert eine breite Vielzahl der Analyse Methodenlehren, Ihnen die größte Flexibilität in der Energie Rasterfeldüberprüfung zu geben. Zum Beispiel wenn die einzigen Verhaltensinformationen, die Sie auf Ihrem Chip haben, ist geschätzte Gesamt-Leistungsaufnahme, Sie kann statische Analyse verwenden, um die Qualität Ihres Energie Rasterfeldes zu überprüfen. Wenn Sie Nettobewegungshäufigkeiten haben, können Sie Aktivität-activity-based Analyse verwenden, um statische Analyse Ihres Energie Rasterfeldes durchzuführen. Sie können die Technologie Accura auch verwenden, um die Machtverteilung Verbrauch für Ihr Chip zu schätzen. Diese Technologie nimmt alle mögliche Energie, Aktivität oder Frequenzdaten, die Sie haben und Schätzungen die restlichen Daten mit statistische Analyse Techniken an. Wenn Sie Repräsentativvektoren für Ihr Design haben, können Sie jene Vektoren simulieren, um ein geschätztes durchschnittliches Verhalten der verschiedenen Teile des Designs für statische Analyse zu erhalten. Wenn Sie Vektoren, die Sie wissen, können IR Tropfen beeinflussen blocken insbesondere von Ihrem Design haben, können Sie tran durchführen wünschen

[Chipdesign]

A New Angle on Chip Design

By Brian Caulfield, October 2001 Issue







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For decades microchip design has followed strict "Manhattan" architecture: millions of transistors, arrayed like city blocks and surrounded by tiny streets and avenues of aluminum or copper wire, or interconnects. But while engineers continue to keep pace with Moore`s Law -- finding ways to double the transistor capacity of a single chip about once every 18 months -- the 90-degree-angle wiring plan to connect all those transistors is reaching its upper limit.

Simplex Solutions, which sells software used to design chips, recently announced a new chip-wiring scheme that could help engineers continue their assault on computing-power records. The company`s new "X architecture" allows a chip`s interconnects to be laid down at 45-degree angles. That seemingly simple trick would allow chips to run 10 percent faster and consume 20 percent less power. It would also allow manufacturers to produce 30 percent more working chips per wafer, claims Simplex CTO Steve Teig. That`s because 45-degree angles allow shorter, more direct connections between transistors, thus reducing the distance electrons have to travel.


Teig says the new design will likely be of most interest first to those producing very specialized, high-performance chips for tasks like digital signal processing and image rendering. Such chips -- being developed by members of the X-Initiative, a trade group Simplex has formed around its new technology -- are already on the way. Toshiba has announced that it will produce the first commercial X-architecture chip next year.





http://www.business2.com/articles/mag/0,1640,16901,FF.html

[Chipdesign]

TSMC Delivers First 0.13-Micron Interconnect Calibration Platform
Unique Design Capability Provides Parasitics Data to Enable Right-the-First-Time Design
HSIN-CHU, Taiwan--(BUSINESS WIRE)--Oct. 24, 2001--Taiwan Semiconductor Manufacturing Company (TSMC) has developed a unique Calibration Platform that helps designers quickly and easily validate new designs. Based on TSMC`s industry-leading, all-copper and low-k dielectric, 0.13-micron process, the Calibration Platform compiles highly reliable engineering data from leading electronic design automation (EDA) vendors, including Sequence Design Inc., Simplex Solutions Inc. and Synopsys Inc..

``TSMC`s 0.13-micron process clearly leads the industry in number of design starts and volume of manufacturing,`` said Genda Hu, TSMC vice president of corporate marketing. ``The 0.13-micron Interconnect Calibration Platform extends this leadership by providing direct access to more calibration and correlation data than any other foundry. This significantly increases designers` confidence that their silicon will work the first time, exactly as planned.``

Dr. Hu added that the project has been so successful that TSMC is expanding the program, including more vendors and entirely new classes of data -- such as inductance -- for TSMC`s 0.10-micron industry standard process.

TSMC`s unique 0.13-micron Interconnect Calibration Platform was created in test chip form and delivered to leading EDA vendors in March 2000. These companies then used the platform`s parasitic extraction data to speed the development of validation tools for 0.13-micron design in TSMC`s process.

The result of this exercise is a common Calibration Platform for TSMC`s 0.13-micron copper process. The Calibration Platform provides a stable, highly-defined validation methodology that is consistent and accurate, no matter which vendor tool sets are used. Supported extraction toolsets include Arcadia® from Synopsys, Columbus® from Sequence, and Fire & Ice® QX from Simplex.

``We worked with the major EDA vendors to verify that the interconnect extraction results from their tools are accurate with silicon data from TSMC`s most advanced 0.13-micron process,`` said Dr. Andrew Moore, marketing manager, EDA relations for TSMC. ``The results allow designers to fully utilize the benefits of the low-k dielectric and eight layers of copper interconnect offered in TSMC`s 0.13-micron process.``

About TSMC

TSMC is the world`s largest dedicated semiconductor foundry, providing the industry`s leading process technology and the foundry industry`s largest portfolio of process-proven library, IP, design tools and reference flows. The company operates two advanced 300mm wafer fabs, seven eight-inch fabs and two six-inch wafer fabs. TSMC also has substantial capacity commitments at two joint ventures fabs (Vanguard and SSMC) and at its wholly-owned subsidiary, WaferTech. In early 2001, TSMC became the first IC manufacturer to announce a 0.10-micron technology alignment program with its customers. TSMC`s corporate headquarters are in Hsin-Chu, Taiwan. For more information about TSMC please go to http://www.tsmc.com.

Editor`s note: All trademarks are the intellectual property of their respective owners.


--------------------------------------------------------------------------------
Contact:

TSMC North America
Dan Holden, 408/382-8000
Cell phone: [phone]
[e-mail]


http://biz.yahoo.com/bw/011024/240483_1.html

[Chipdesign]

Simplex, Toshiba Team to Build Faster, Cheaper Chips (Update3)
By Michael Lovell


Sunnyvale, California, June 4 (Bloomberg) -- Simplex Solutions Inc., the semiconductor-software maker whose shares have more doubled in the past month, and No. 2 chipmaker Toshiba Corp. have created a new way to build faster and more efficient chips.

Shares of Simplex, based in Sunnyvale, California, rose $10.20, or 36 percent, to $38.20. They`ve more than tripled since the company first sold 4 million shares at $12 each on May 1, raising $48 million for the company. Toshiba fell 8 yen to 675 ($5.66) in Tokyo today. They`ve fallen 12 percent this year.

Simplex`s software helps design and produce semiconductors. The new process, which Simplex and Toshiba have been working on for two years, will let chip designers create semiconductors that are 10 percent faster while using 20 percent less power, Chief Executive Penny Herscher said in an interview.

The new design will let information on chips travel diagonally, instead of at right angles, as current chip designs allow for, Herscher said. The new process will also let chipmakers build 30 percent more chips on a single silicon wafer.

``This will change the face of silicon,`` Herscher said. ``It will change the way every chip looks five years from now.``

Simplex said it will be able to create a limited number of so- called X architecture chips this year. Toshiba, based in Tokyo, plans to use the new chips in electronic devices in 2002.

Simplex`s customers include No. 1 computer-chip maker Intel Corp., Advanced Micro Devices Inc., the second-biggest maker of computer chips, and STMicroelectronics NV, Europe`s No. 1 semiconductor maker.

Separately, Simplex said it joined with several semiconductor- related companies to promote use of the new chip design. Those companies include Dai Nippon Printing, DuPont Photomasks Inc., Applied Materials Inc., KLA-Tencor Corp., Numerical Technologies Inc., PDF Solutions Inc., Tensilica Inc. and Virtual Silicon Technology Inc.

http://quote.bloomberg.com/fgcgi.cgi?T=marketsquote99_news.h…

[Chipdesign]

Cadence to Offer Simplex Extraction Technology
Exclusive Agreement to Provide World-Class Gate-Level Extraction Solution
SAN JOSE, Calif.--(BUSINESS WIRE)--Jan. 16, 2002--Cadence Design Systems, Inc. (NYSE:CDN - news), the world`s leading supplier of electronic design products and services, and Simplex Solutions, Inc. (Nasdaq:SPLX - news), a leading provider of software and services for the design and verification of integrated circuits, today announced a technology-licensing agreement that gives Cadence exclusive distribution rights to the Simplex standalone parasitic extraction technology, Fire & Ice® QX. The agreement addresses customers` requirements for fast, accurate parasitic extraction by incorporating Simplex extraction technology as part of the Cadence® advanced deep submicron solution -- the industry`s most complete design flow. Financial terms of the four-year agreement were not disclosed.

``This is another example of Cadence and the electronic design industry working together to better serve the complete spectrum of our customers` needs,`` said Lavi Lev, executive vice president and general manager of IC Solutions at Cadence. ``We always look for great technology to enhance our design flow. Simplex`s Fire & Ice QX is the best gate-level extraction technology available and will work well within our industry-leading SP&R design solution.``

Simplex retains the rights to continue to directly sell and support current and future SoC verification products with embedded extraction technologies.

``Cadence offers first-class sales and support in the global EDA industry. We are delighted to have Cadence market our extraction technology,`` said Penny Herscher, chairman and CEO of Simplex. ``Distribution of our Fire & Ice QX through the Cadence worldwide channel will dramatically expand customer access to this key technology.``

Fire & Ice QX for gate-level design is complementary to the Cadence Diva® and Assura(TM) Parasitic Extractor (RCX) technology for custom integrated circuit design.

About Cadence

Cadence is the largest supplier of electronic design technologies, methodology services, and design services. Cadence solutions are used to accelerate and manage the design of semiconductors, computer systems, networking and telecommunications equipment, consumer electronics, and a variety of other electronics-based products. With approximately 5,700 employees and 2000 revenues of approximately $1.3 billion, Cadence has sales offices, design centers, and research facilities around the world. The company is headquartered in San Jose, and traded on the New York Stock Exchange under the symbol CDN. More information about the company, its products, and services is available at www.cadence.com.

About Simplex

Simplex Solutions (TM), Inc. provides software and services for the design and verification of integrated circuits to enable its communications, computer, and consumer-products customers to achieve first-time production success and rapid delivery of complex systems-on-chip. Simplex customers use its products and services prior to manufacture to design and verify the integrated circuits to help ensure that the integrated circuits will perform as intended, taking into account the complex effects of deep-submicron semiconductor physics. Simplex can be reached at 408/617-6100 or on the web at www.simplex.com.

Cautionary Note Regarding Forward-looking Statements

This release contains forward-looking statements (including, without limitation, information regarding the ability of the agreement to address and serve Cadence customers` requirements, the successful incorporation of Simplex technology into the Cadence design solution, Simplex expectation to develop future SoC verification products, Cadence intention to market and distribute Simplex extraction technology, and the expansion of customer access into Simplex Fire & Ice QX technology) that involve risks and uncertainties that could cause the results of Cadence and Simplex to differ materially from management`s current expectations.

Actual results may differ materially due to a number of factors including, among others: future strategic decisions made by Simplex and/or Cadence; competitive developments; demand for Simplex Fire & Ice QX technology and the Cadence design solutions; demand for advanced semiconductor chips and verification software that supports their production; and the rapid pace of technological change in the semiconductor industry. The matters discussed in this press release also involve risks and uncertainties described in the most recent filings of Cadence and Simplex with the Securities and Exchange Commission. Cadence and Simplex assume no obligation to update the forward-looking information contained in this release.

Note to Editors: Fire & Ice is a registered trademark, and Simplex Solutions and the Simplex logo are trademarks of Simplex Solutions, Inc. Cadence, the Cadence logo, and Diva are registered trademarks, and Assura is a trademark of Cadence Design Systems, Inc. All other trademarks mentioned in this press release are the properties of their respective owners.



--------------------------------------------------------------------------------
Contact:

Cadence Design Systems, Inc.
Judy Erkanat, 408/894-2302
[e-mail]
or
Simplex Solutions, Inc.
Janet Greene, 408/617-6195
[e-mail]

[Chipdesign]

Simplex Solutions Reports Financial Results for First Fiscal Quarter of 2002
SUNNYVALE, Calif., Jan. 17 /PRNewswire-FirstCall/ -- Simplex Solutions, Inc. (Nasdaq: SPLX - news), today reported its first quarter fiscal year 2002 results for the period ended December 31, 2001. Simplex reported revenue of $11.1 million and pro forma net income of $76,000, or $0.00 per share. Pro forma net income excludes stock-based compensation expense and amortization of acquired intangible assets. This compares to revenue of $9.2 million and pro forma net income of $49,000, or $0.00 per share for the first quarter of fiscal 2001.

Financial results prepared in accordance with generally accepted accounting principles (GAAP) are shown below.

``Simplex has an excellent market opportunity, despite the tough environment created by the slowdown in the semiconductor industry and the economy,`` said Penny Herscher, chairman and CEO of Simplex Solutions, Inc. ``Our product offerings continue to provide us with a solid leadership position in the SoC verification market. With the additional investments that we are making in R&D, we believe that we are well positioned to take advantage of an economic recovery.``

Simplex will hold a conference call that includes a business outlook, with financial analysts and investors, today at 2:00 p.m. PST. A live webcast of the call will be available on Simplex`s Web site at www.simplex.com or at www.companyboardroom.com. Following completion of the call, a rebroadcast of the webcast will be available at www.simplex.com or www.companyboardroom.com through January 25, 2002. For those without access to the Internet, a replay of the call will be available beginning at 5:00 p.m. PST on January 17, 2002, through January 25, 2002. To listen to the replay, call 719-457-0820, access code 708723.

Cautionary Note Regarding Forward-looking Statements

This release contains forward-looking statements (including, without limitation, our market opportunity, our continued leadership position in SoC verification and our perceived positioning in the event of an economic recovery) that involve risks and uncertainties that could cause the results of Simplex to differ materially from management`s current expectations.

Actual results may differ materially due to a number of factors, including, among others: future strategic decisions made by Simplex; competitive developments; general economic conditions; demand for advanced semiconductor chips and verification software that supports their production; and the rapid pace of technological change in the semiconductor industry. The matters discussed in this press release also involve risks and uncertainties described in Simplex`s most recent filings with the Securities and Exchange Commission. Simplex assumes no obligation to update the forward-looking information contained in this release.

About Simplex

Simplex Solutions, Inc. provides software and services for the design and verification of integrated circuits (ICs) to enable its communications, computer and consumer-products customers to achieve first-time production success and rapid delivery of complex systems-on-chip. Simplex`s customers use its products and services prior to manufacture to design and verify ICs and help ensure they will perform as intended, taking into account the complex effects of deep-submicron semiconductor physics. Simplex can be reached at 408-617-6100 or on the web at www.simplex.com.


Simplex Solutions, Inc.
Pro Forma Condensed Consolidated Statements of Operations (A)
(in thousands, except per share data)
(Unaudited)

Three Months
Ended
December 31, December 31,
2001 2000
Revenue:
Software
Software-License $5,329 $4,281
Software-Service 2,836 2,680
Design foundry 2,947 2,213
11,112 9,174
Costs of Revenue:
Cost of software 12 2
Cost of service 468 1,087
Cost of design 2,075 1,348
Total cost of revenue 2,555 2,437

Gross Margin 8,557 6,737

Expenses:
Selling and marketing 4,244 3,118
Research and development 3,360 2,238
General and administrative 1,289 1,135
8,893 6,491

Income (loss) from operations (336) 246

Interest and other income 524 99
Interest expense (1) (111)

Income before income taxes 187 234

Provision for income taxes 111 185

Net Income $76 $49


Basic net income per share $0.01 $0.01

Fully diluted proforma net income per
share $0.00 $0.00

Number of shares used in calculation
of basic net income per share 14,867 5,405
Number of shares used in calculation
of diluted proforma net income per share 16,761 11,418

(A) Pro forma net income excludes the impact of amortization of
acquired intangibles and stock-based compensation.


Simplex Solutions, Inc.
Condensed Consolidated Statements of Operations
(in thousands, except per share data)
(Unaudited)

Three Months
Ended
December 31, December 31,
2001 2000
Revenue:
Software
Software-License $5,329 $4,281
Software-Service 2,836 2,680
Design foundry 2,947 2,213
11,112 9,174
Costs of Revenue:
Cost of software 12 2
Cost of service 468 1,087
Cost of design 2,075 1,348
Total cost of revenue 2,555 2,437

Gross Margin 8,557 6,737

Expenses:
Selling and marketing 4,244 3,118
Research and development 3,360 2,238
General and administrative 1,289 1,135
Amortization of acquired
intangibles 113 1,639
Stock-based compensation 1,055 2,545

10,061 10,675

Loss from operations (1,504) (3,938)

Interest and other income 524 99
Interest expense (1) (111)

Loss before income taxes (981) (3,950)

Provision for income taxes 111 185

Net Loss $(1,092) $(4,135)

Basic net loss per share $(0.07) $(0.77)

Number of shares used in calculation
of basic
net loss per share 14,867 5,405


Simplex Solutions, Inc.
Condensed Consolidated Balance Sheet
(in thousands)



December 31, September 30,
2000 2001(A)
(Unaudited)


Cash, cash equivalents and
short-term investments 54,109 50,671
Accounts receivable 11,425 17,237
Prepaid expenses and other current
assets 1,393 1,588

Total current assets 66,927 69,496

Property and equipment, net 5,798 5,114
Other assets 454 458
Intangible assets, net 24,260 24,379

Total assets 97,439 99,447

Accounts payable 579 1,859
Accrued liabilities 2,068 2,008
Accrued payroll and related expenses 4,116 5,784
Deferred revenue 6,926 7,781
Total current liabilities 13,689 17,432

Other long term liabilities 122 122
Note payable 146 150
Total liabilities 13,957 17,704


Common stock 15 15
APIC 132,191 130,317
Notes receivable from stockholders (1,022) (1,283)
Unearned stock-based compensation (5,671) (6,725)
Accumulated other comprehensive
income (loss) (312) 46
Accumulated deficit (41,719) (40,627)

Total stockholders` equity 83,482 81,743

Total liabilities and
stockholders` equity 97,439 99,447


(A) Derived from audited financial statements as of September 30, 2001.

SOURCE: Simplex Solutions, Inc.

[optical]

07:32 ET Simplex Solutions upped by Robbie, price target cut (SPLX) 7.95: Robertson Stephens upgrades to BUY from Mkt Perform due to valuation; firm believes that potential catalysts for the stock could be the upcoming announcements regarding the X Architecture over the coming qtrs. Lowers price target to $12 from $15.

[optical]

07:32 ET Simplex Solutions upped by Robbie, price target cut (SPLX) 7.95: Robertson Stephens upgrades to BUY from Mkt Perform due to valuation; firm believes that potential catalysts for the stock could be the upcoming announcements regarding the X Architecture over the coming qtrs. Lowers price target to $12 from $15.

[optical]

07:32 ET Simplex Solutions upped by Robbie, price target cut (SPLX) 7.95: Robertson Stephens upgrades to BUY from Mkt Perform due to valuation; firm believes that potential catalysts for the stock could be the upcoming announcements regarding the X Architecture over the coming qtrs. Lowers price target to $12 from $15.

[Chipdesign]

Virage and NurLogic Join Simplex`s IP Power Grid Library Program
Leading IP Providers Build Momentum for Pre-verified Power Grid Libraries
SUNNYVALE, Calif., March 4 /PRNewswire-FirstCall/ -- Simplex Solutions, Inc. (Nasdaq: SPLX - news), a leading provider of software and services for the design and verification of integrated circuits (ICs), today announced that NurLogic Design, Inc. (San Diego, Calif.) and Virage Logic (Nasdaq: VIRL - news) have joined Simplex`s intellectual property (IP) power grid library program, building momentum for the inclusion of pre-verified power grid libraries with leading IP libraries and components. As participants in Simplex`s industry-leading program, NurLogic, a developer of high bandwidth connectivity IP solutions, and Virage Logic, a leader in embedded memory solutions, will deliver their IP with pre-validated power grid libraries for use in verifying the power grid integrity of complex system-on-chip (SoC) designs. The libraries will be used with Simplex`s leading power grid verification product, VoltageStorm(TM) SoC.

The Simplex IP Partners Program is focused on building, pre-validating and distributing transistor-accurate power grid models for leading IP libraries and components, to be used in power grid verification with VoltageStorm SoC. Through their participation in the Simplex program, NurLogic and Virage Logic enable their customers to immediately benefit from the speed of the VoltageStorm SoC`s hierarchical verification approach, while maintaining the transistor-level accuracy required for deep-submicron (DSM) power integrity analysis.

``NurLogic`s innovative and advanced approach to solving SoC challenges has made us a proven leader in IP development,`` said Lisa Lipscomb, vice president of marketing at Nurlogic. ``By verifying the power grid integrity of our high-speed IP and providing power grid libraries with these leading IP solutions, we enable our customers to be more competitive and productive.``

Vincent Ratford, vice president of marketing at Virage Logic, echoed that providing IP with pre-verified power grid libraries has significant value to customers. ``Our leading embedded memory products are optimized for area, speed and power,`` stated Ratford. ``By providing power grid libraries with our memories, our customers can not only have confidence in power grid integrity of our IP, but also use our products more efficiently and effectively in their communications, consumer and computer products.``

Until the advent of DSM process technologies, IR (voltage) drop was considered a second- or third-order effect. Today`s deep-submicron SoC designs, with their increasing chip size and number of integrated IP blocks and decreasing power supply voltages, are at increased risk for IR drop-related failures due to the unpredictable flow of power in and around embedded blocks.

The Simplex IP Partners Program was launched with charter members ARM Ltd. and Virtual Silicon Technologies, Inc. in June 2001 as the industry`s first IP power grid library program. Commenting on the growth of the program, Jan Willis, vice president of business development at Simplex, said, ``From standard cells to memories to cores, Simplex`s IP Partners Program supports all IP with transistor-accurate characterization of the power grid. We`re very pleased to see the momentum of the program building as leading IP suppliers such as NurLogic and Virage recognize and respond to this critical design need.``

Availability

Pre-validated power grid libraries are available by request to NurLogic and VirageLogic customers for select IP products. The VoltageStorm SoC product suite includes tools that enable SoC design teams using custom libraries and IP blocks to create their own power grid libraries.

About the Simplex IP Partners Program

The Simplex IP Partners Program, launched in June 2001 as the industry`s first IP power grid library program, provides users of Simplex`s VoltageStorm SoC power grid verification product with pre-validated power grid libraries for a variety of system-on-chip components, including standard cells, I/Os, embedded processor cores and memories. The pre-validated power grid libraries available through the program provide SoC designers with direct access to VoltageStorm SoC`s fast, hierarchical verification while maintaining the transistor-level accuracy required for deep-submicron power integrity analysis. Current members include ARM Ltd., NurLogic Design, Inc., Virage Logic and Virtual Silicon Technology, Inc.

About NurLogic Design, Inc.

NurLogic Design, Inc. provides high-bandwidth connectivity solutions to the networking and communications industries. NurLogic`s products encompass customer-specific and industry-standard integrated circuits and semiconductor intellectual property to deliver value-add to its customers. NurLogic products are targeted at CMOS and silicon germanium technologies, and include high-speed connectivity IP, analog and mixed-signal IP, foundation IP, and PMD and PHY ICs. NurLogic is the recipient of the 2001 Most Innovative New Product (MIP) Award in a competition sponsored by the University of California-San Diego (UCSD) CONNECT program for its 48-channel optical interface chipset design. Based in San Diego, California, the company has regional sales offices in Massachusetts and Silicon Valley. NurLogic is a privately held corporation. Headquarters: 5580 Morehouse Drive, San Diego, Calif. 92121. Tel: 1-877-NURLOGIC. On the web at www.nurlogic.com.

About Virage Logic

Virage Logic is a technology and market leader in embedded memory. To meet customer design goals with the highest level of quality, Virage Logic products are production tested and optimized for area, power and speed. These products include embedded memory cores, which are critical components of communications, consumer and computer products, including switches, routers, modems, cellular phones, set-top boxes, HDTVs, DVD players and PCs. In addition, the company offers software tools and custom memory design services. The company`s customers include fabless semiconductor companies targeting pure-play foundries and semiconductor companies. Founded in January 1996, the company has over 200 employees and is located at 46501 Landing Pkwy., Fremont, Calif., 94538. Telephone: [phone] (toll free) or 510-360-8000. Fax: [phone]. For more information, please visit www.viragelogic.com.

About Simplex Solutions, Inc.

Simplex Solutions, Inc. provides software and services for the design and verification of integrated circuits to enable its communications, computer and consumer-products customers to achieve first-time production success and rapid delivery of complex systems-on-chip. Simplex`s customers use its products and services prior to manufacture to design and verify the integrated circuits to help ensure that the integrated circuits will perform as intended, taking into account the complex effects of deep-submicron semiconductor physics. Simplex can be reached at 408-617-6100 or on the web at www.simplex.com.

Cautionary Note Regarding Forward-looking Statements

This release contains forward-looking statements (including, without limitation, information regarding the benefits of Simplex`s IP Partners Program, the ability of Simplex`s IP Partners Program to support all IP, the timing of availability of pre-validated power grid libraries and the ability of SoC design teams using custom libraries and IP blocks to create their own power grid libraries) that involve risks and uncertainties that could cause the results of Simplex to differ materially from management`s current expectations.

Actual results may differ materially due to a number of factors including, among others: future strategic decisions made by Simplex, NurLogic, Virage Logic and other program members; competitive developments; demand for advanced semiconductor chips and the verification software that supports their production; the availability of pre-validated power grid libraries through the program, members` continued involvement in the program, the ability of power grid libraries provided through the program to integrate with third party custom IP; and the rapid pace of technological change in the semiconductor industry. The matters discussed in this press release also involve risks and uncertainties described in Simplex`s most recent filings with the Securities and Exchange Commission. Simplex assumes no obligation to update the forward- looking information contained in this release.

NOTE: Simplex Solutions, the Simplex logo and VoltageStorm are trademarks of Simplex Solutions. All other trademarks mentioned here are the property of their respective owners.

SOURCE: Simplex Solutions, Inc.

[Chipdesign]

Dai Nippon Printing Confirms New Supply Chain for X Architecture Masks
Results Using Toshiba Machine Equipment Prove Viability Of Vector-Based Systems
SUNNYVALE, Calif., March 4 /PRNewswire-FirstCall/ -- The X Initiative, a semiconductor supply-chain consortium, and Dai Nippon Printing (DNP), one of the world`s largest comprehensive printing companies, today announced the results of a successful effort by charter members DNP and Simplex Solutions, Inc. (Nasdaq: SPLX - news) to confirm a new supply chain for X Architecture photomasks. Using X Architecture design data supplied by Simplex, DNP demonstrated for the first time the viability of vector-based, mask-pattern generation equipment for producing X Architecture photomasks. DNP employed existing vector-based equipment from charter member Toshiba Machine Company, Ltd. (Tokyo, Japan) to successfully write an X Architecture test mask without significant runtime or data volume increases, as compared to raster-based mask pattern generation methods.

Earlier experiments by X Initiative members confirmed that advanced raster-based mask pattern generation systems are well suited for writing X Architecture masks. DNP`s results address the important question of whether vector-based systems could also efficiently write X Architecture masks without undue impact on runtimes. Previous-generation vector-based systems, which exclusively employed rectangular apertures, are optimized for right-angle interconnects. In contrast, Toshiba Machine`s EBM-3000/3500 mask-pattern generation equipment employs triangular apertures to address diagonals, alleviating the problems associated with vector-based writing of diagonal lines. DNP`s results will help accelerate the adoption of the X Architecture as a production-worthy approach to the pervasive use of diagonal interconnect, which drives a host of benefits, including improved chip performance, power consumption and number of working chips per wafer.

Using 0.18-micron design data in GDSII format supplied by Simplex and fractured using Numerical Technologies` de facto standard CATS(TM) mask data preparation software, DNP was able to analyze the mask produced by the Toshiba Machine equipment with LWM-250UV CD metrology equipment from Leica Microsystems AG, and inspect it with a KLA-Tencor 353UV inspection system.

After inspecting the mask and evaluating the impact on runtimes and data sizes, Naoya Hayashi, departmental general manager of research in the Semiconductor Components Laboratory at DNP, said, ``We are very pleased to confirm that existing equipment from both of our primary mask-pattern generation equipment suppliers, Etec Systems and Toshiba Machine, support the X Architecture. The X Initiative is providing a valuable resource for determining the readiness of the supply chain to support this new breakthrough. We anticipate no issues in working with customers to support the X Architecture.``

Commenting on the significance of these efforts, Jan Willis, vice president of business development at Simplex Solutions and X Initiative steering group facilitator, said, ``We are pleased that over 75 percent of the suppliers in the mask segment are members of the X Initiative. Thanks to the efforts of X Initiative members, like DNP, we now have confirmed the viability of multiple supply chains for the X Architecture, which maximizes the market for the X Architecture.``

About Dai Nippon Printing Co., Ltd.

Dai Nippon Printing (DNP) is one of the world`s largest comprehensive printing companies, with annual sales of 1.342 trillion yen and 34,000 employees (as of March 2001). DNP`s wide range of businesses include publication printing, commercial printing, smart cards, business forms, network business and electronic components. While DNP maintains a 50 percent market share in Japan`s domestic magazine printing, the company continues to leverage its information processing techniques and printing technologies to promote cross-media solutions. DNP accounts for about 40 percent of Japan`s photomask market and 25 percent of the world market. For more information about DNP, please visit www.dnp.co.jp

About the X Architecture

The X Architecture, the first production-worthy approach to the pervasive use of diagonal interconnect, reduces the total interconnect, or wiring, on a chip by more than 20 percent. Based on initial evaluations, this wire-length reduction is expected to deliver simultaneous improvements of 10+ percent greater chip performance, 20+ percent less power dissipation, and 30+ percent more chips per wafer for complex, multiple-metal-layer ICs such as systems-on-chip (SoCs). For the past 20 years, chip design has been primarily based on the de facto industry standard ``Manhattan`` architecture, named for its right-angle interconnects resembling a city-street grid. The X Architecture rotates the primary direction of the interconnect in the fourth and fifth metal layers by 45 degrees from a Manhattan architecture. The new architecture maintains compatibility with existing cell libraries, memory cells, compilers and IP cores by preserving the Manhattan geometry of metal layers one through three.

About the X Initiative

The X Initiative, a group of leading companies from throughout the semiconductor industry, is chartered with accelerating the availability and fabrication of the X Architecture, a revolutionary interconnect architecture based on the pervasive use of diagonal routing. The X Initiative`s five-year mission is to provide an independent source of education about the X Architecture, to facilitate support and fabrication of the X Architecture through the semiconductor industry supply chain, and to survey usage of the X Architecture to track its adoption. Representing leaders spanning the entire design-to-silicon infrastructure, X Initiative members include: Artisan Components, Inc.; Dai Nippon Printing (DNP); DuPont Photomasks, Inc.; Etec Systems, Inc., an Applied Materials, Inc. company; HPL Technologies, Inc.; KLA-Tencor Corporation; Leica Microsystems AG; Matsushita Electric Industrial Co., Ltd.; MicroArk Co. Ltd.; Monterey Design Systems, Inc.; Numerical Technologies, Inc.; NurLogic Design, Inc.; PDF Solutions, Inc.; Photronics Inc.; Prolific Inc.; RUBICAD Corporation; Sagantec; Sanyo Electric Co., Ltd.; Silicon Logic Engineering, Inc.; SiliconMap, LLC.; Silicon Perspective Corp.; Silicon Valley Research Inc.; Simplex Solutions, Inc.; STMicroelectronics; Sycon Design, Inc.; Tensilica, Inc.; Toppan Printing Co.; Toshiba Machine Co., Ltd.; Toshiba Corporation; Virage Logic, Inc.; Virtual Silicon Technology, Inc.; and Zygo Corporation. Membership is open to all companies throughout the semiconductor supply chain. Materials can be found at www.xinitiative.org .

Cautionary Note Regarding Forward-looking Statements

This release contains forward-looking statements (including, without limitation, information regarding semiconductor design, production and performance improvements resulting from the X Architecture, the compatibility of the X Architecture with current production equipment, information that the test results will help accelerate the adoption of the X Architecture, and the ability of certain of the X Initiative members to support the X Architecture) that involve risks and uncertainties that could cause the results of X Initiative members and other events to differ materially from managements` current expectations.

Actual results and events may differ materially due to a number of factors, including, among others: future strategic decisions made by X Initiative members or others that inhibit the development of the X Architecture; failure of the X Architecture to enable the production of designs that are feasible and competitive with current designs or future alternatives; demand for advanced semiconductors that are developed using the X Architecture; cost feasibility of the production of semiconductors designed using the X Architecture; and the rapid pace of technological change in the semiconductor industry. The matters discussed in this press release also involve risks and uncertainties described in the most recent filings of the X Initiative members with the Securities and Exchange Commission. The X Initiative members assume no obligation to update the forward-looking information contained in this release.

SOURCE: Simplex Solutions, Inc.

[Chipdesign]

Simplex Delivers First-Silicon Success for Infineon`s Titan 19244, World`s First Single-Chip 40Gbps Framer-Mapper Device
Simplex`s SoC Design Foundry Teams with TSMC on Blockbuster Optical-Networking Chip
SUNNYVALE, Calif., March 11 /PRNewswire-FirstCall/ -- Industry leaders Simplex Solutions, Inc. (Nasdaq: SPLX - news), Infineon Technologies (NYSE: IFX; FSE) and Taiwan Semiconductor Manufacturing Company (NYSE: TSM; TSMC) today announced the details of their collaboration that delivered Infineon`s recently unveiled Titan 19244, the world`s first single-chip 40Gbps framer-mapper device for next-generation optical-networking applications. Simplex`s SoC Design Foundry team helped to engineer the physical implementation for Infineon`s groundbreaking design, which was fabricated by TSMC. Through the three companies` cooperative efforts, the complex, high-performance optical-networking chip performed to specification on first silicon.

The design for the Titan 19244 was originally developed by Catamaran Communications, which Infineon acquired in April 2001. Catamaran was referred to the Simplex SoC Design Foundry through TSMC`s Design Center Alliance (DCA) program, a resource for customers requiring leading-edge design services.

``When we met with Simplex`s SoC Design Foundry team, it was obvious that they were the most qualified team to create the physical implementation of our design,`` said Vijay Mehra, vice president, VLSI engineering at Infineon-Catamaran. ``The first-silicon results speak for themselves. The TSMC DCA provided much-needed support for matching us with the strategic partner we needed for this immense task.``

Collaboration Details

Simplex`s SoC Design Foundry design team employed a hierarchical physical design methodology to deliver first-silicon success for the Titan 19244, the first system-on-chip (SoC) with a data-transfer rate of 10Gbps X 4 / 40Gbps. The chip has more than 50 clock domains, with operating frequencies ranging from approximately 77MHz to 700MHz.

The SoC Design Foundry team, working closely with Infineon`s engineering team, achieved timing closure leveraging Simplex`s SignalStorm(TM) SoC for hierarchical delay calculation -- resulting in close correlation to SPICE. Voltage (IR) drop analysis, performed with Simplex`s VoltageStorm(TM) SoC power-grid verification tool, showed voltage drop well within the parameters of the specification.

TSMC manufactured the chip using its 0.15-micron low-voltage CMOS process technology with eight layers of metal, including a redistribution layer for bumps-to-I/O pad distribution. A custom substrate design, specified by Infineon for a 1,413-pin flip-chip ball-grid array (BGA) package, was used to achieve the chip`s target performance and handle the dense high-speed I/O interfaces.

``The mission of TSMC`s Design Center Alliance, which now includes 28 partner companies worldwide, is to provide our customers with the quality design support they need to succeed,`` said Genda Hu, vice president of marketing at TSMC. ``Simplex implemented Infineon`s design in TSMC`s 0.15-micron silicon process with first-pass success, clearly demonstrating the value of TSMC`s Design Center Alliance to our customers.``

Aurangzeb Khan, Simplex executive vice president and general manager of the company`s SoC Design Foundry, noted, ``Our mission is to provide our customers with the critical market advantage of first-silicon success for their most complex designs. Working with a `world`s-first` design like the Infineon Titan 19244, presents us with exactly the kind of complex technical challenge that our design methodology was built to address and that our engineers thrive upon. We are very pleased to be able to contribute to the success of this pioneering chip design.``

About Infineon

Infineon Technologies AG, Munich, Germany, offers semiconductor and customized solutions for applications in the wired and wireless communications markets, for security systems and smart cards, for the automotive and industrial sectors, as well as memory products. With a global presence, Infineon operates in the US from San Jose, CA, in the Asia-Pacific region from Singapore and in Japan from Tokyo. In the fiscal year 2001 (ending September), the company achieved sales of Euro 5.67 billion with about 38,800 employees worldwide. Infineon is listed on the DAX index of the Frankfurt Stock Exchange and on the New York Stock Exchange (ticker symbol: IFX). Further information is available at www.infineon.com

About TSMC

TSMC is the world`s largest dedicated semiconductor foundry, providing the industry`s leading process technology and the foundry industry`s largest portfolio of process-proven library, IP, design tools and reference flows. The company has one advanced 300mm wafer fab in production and one under construction, in addition to seven eight-inch fabs and two six-inch wafer fabs. TSMC also has substantial capacity commitments at two joint ventures fabs (Vanguard and SSMC) and at its wholly-owned subsidiary, WaferTech. In early 2001, TSMC became the first IC manufacturer to announce a 0.10-micron technology alignment program with its customers. TSMC`s corporate headquarters are in Hsin-Chu, Taiwan. For more information about TSMC please go to http://www.tsmc.com

About Simplex

Simplex Solutions, Inc. provides software and services for the design and verification of integrated circuits to enable its communications, computer and consumer-products customers to achieve first-time production success and rapid delivery of complex systems-on-chip. Simplex`s customers use its products and services prior to manufacture to design and verify the integrated circuits to help ensure that the integrated circuits will perform as intended, taking into account the complex effects of deep-submicron semiconductor physics. Simplex can be reached at [phone] or on the web at www.simplex.com

SOURCE: Simplex Solutions, Inc.

[Chipdesign]

Tuesday March 19, 9:44 pm Eastern Time
Simplex signs memorandum of understanding on IP dispute
NEW YORK, March 19 (Reuters) - Simplex Solutions Inc. (NasdaqNM:SPLX - news), a maker of software for chip design and verification, said on Tuesday it has signed a memorandum of understanding with Sequence Design Inc. pertaining to their patent dispute.

The terms of the memorandum of understanding are confidential, Simplex said, however, they involve an exchange of certain specified intellectual property rights and other financial considerations.

Simplex said the terms are not material to its financial results.

Sequence brought a patent infringement suit against Simplex in August, 2001.

As a result of the deal, the U.S. District Court in Oakland, Calif. has issued a conditional order of dismissal, Simplex said. The suit is therefore dismissed contingent upon both parties finalizing a settlement agreement and abiding by the terms of that agreement.

Shares of Simplex rose 9 cents to $9.54 on the Nasdaq on Tuesday.

[Chipdesign]

NEC Deploys Simplex VoltageStorm SoC(TM) for Power Sign-Off
Multi-Million Dollar Deal Makes Simplex a Principal Part of High-End ASIC Design Flow
SUNNYVALE, Calif., April 15 /PRNewswire-FirstCall/ -- Simplex Solutions, Inc., (Nasdaq: SPLX - news), a leading provider of software and services for the design and verification of integrated circuits (ICs), today announced that NEC Corporation (NEC) (Nasdaq: NIPNY; FTSE: 6701q.l; TYSE: 6701) has made a major purchase of Simplex`s VoltageStorm(TM) SoC power grid verification product for power grid sign-off. The multi-million-dollar, three-year agreement makes Simplex`s SoC verification a mandatory part of NEC`s high-end ASIC flow to help ensure first-time working silicon for NEC`s customers` complex system-on-chip (SoC) designs.

``At 0.18-micron and finer process technologies, power-grid design is critical, as voltage drop affects not only chip integrity but also timing. Simplex`s VoltageStorm SoC enables our design centers to produce the highest-performance power grids with confidence,`` said Mr. Yoshitada Fujinami, chief manager, System LSI Design Engineering Division at NEC Electron Devices.

Until the advent of deep-submicron process technologies, IR drop was considered a second- or third-order effect. Today`s high-performance SoC designs, with their increasing chip size and number of integrated IP blocks, as well as decreasing power supply voltages, are at increased risk for IR drop-related failures due to the unpredictable flow of power in and around embedded blocks. Accordingly, SoC designers require verification tools with an embedded transistor-level engine for accuracy combined with automated, hierarchical model generation to rapidly provide a solution to the timing, power and signal-integrity issues.

Fujinami said, ``Transistor-level IP such as embedded DRAM, SRAM, and high-performance logic functions often comprise over 50% of the area of our customers` SoC designs. Simplex`s VoltageStorm SoC is well designed to verify the power grid integrity of these complex SoCs in hierarchical manner. Our ASIC flow also requires the fast runtimes and superior quality that VoltageStorm SoC can provide.``

``NEC understands that its customers` complex SoC designs are vulnerable to the effects of IR drop,`` observed Jim Bailey, general manager of Simplex`s SoC verification business. ``By making power grid sign-off with VoltageStorm SoC part of NEC`s standard flow, they are taking a crucial step to ensure first-time working silicon for their customers.``

About NEC Corporation

NEC Corporation is a leading provider of Internet solutions, dedicated to meeting the specialized needs of its customers in the key computer, network and electron device fields through its three market-focused in-house companies: NEC Solutions, NEC Networks and NEC Electron Devices. NEC Corporation, with its in-house companies, employs more than 150,000 people worldwide and saw net sales of 5,409 billion Yen (approx. US$50 billion) in fiscal year 2000-2001. For further information, please visit the NEC home page at: http://www.nec.com .

About Simplex

Simplex Solutions, Inc. provides software and services for the design and verification of integrated circuits (ICs) to enable its communications, computer and consumer-products customers to achieve first-time production success and rapid delivery of complex systems-on-chip. Simplex`s customers use its products and services prior to manufacture to design and verify ICs to help ensure that they will perform as intended, taking into account the complex effects of deep-submicron semiconductor physics. Simplex can be reached at 408-617-6100 or on the web at www.simplex.com.

Cautionary Note Regarding Forward-Looking Statements

This release contains forward-looking statements (including, without limitation, information regarding the speed, quality and capabilities of VoltageStorm SoC) that involve risks and uncertainties that could cause the results of Simplex to differ materially from management`s current expectations.

Actual results may differ materially due to a number of factors including, among others: future strategic decisions made by Simplex and/or NEC; competitive developments; demand for advanced semiconductor chips and the verification software that supports their production; and the rapid pace of technological change in the semiconductor industry. The matters discussed in this press release also involve risks and uncertainties described in Simplex`s most recent filings with the Securities and Exchange Commission. Simplex assumes no obligation to update the forward-looking information contained in this release.

NOTE: Simplex Solutions, the Simplex logo, and VoltageStorm are trademarks of Simplex Solutions. All other trademarks mentioned in this press release are the properties of their respective owners.

Tell Us What You Think -- Click Here

SOURCE: Simplex Solutions, Inc.

[Chipdesign]

Simplex Solutions Reports Financial Results For Second Quarter 2002
SUNNYVALE, Calif., April 18 /PRNewswire-FirstCall/ -- Simplex Solutions, Inc. (Nasdaq: SPLX - news), today reported its second quarter fiscal 2002 results for the period ended March 31, 2002. Simplex reported revenue of $9.9 million and pro forma net loss of $2.6 million or a loss of $0.17 per share. Pro forma net loss excludes stock-based compensation expense and amortization of acquired intangible assets. This compares to revenue of $11.7 million and pro forma net income of $169,000 or $0.01 per share for the second quarter of fiscal 2001.

For the six-month period ended March 31, 2002, revenue was $21.0 million and pro forma net loss was $2.6 million or a loss of $0.18 per share. For the six-month period ended March 31, 2001, revenue was $20.8 million and pro forma net income was $219,000 or $0.02 per share.

Financial results prepared in accordance with generally accepted accounting principles (GAAP) are shown below.

``While the market environment remained difficult throughout the second quarter, we completed several important milestones for the company, including the launch of our SignalStorm(TM) SOC product and the completion of our OEM agreement with Cadence,`` said Penny Herscher, Simplex`s chairman and CEO. ``These achievements and our customers` continued advance to 0.13-micron process technologies contributed positively to quarterly revenue and the company`s future growth and visibility. Additionally, I`m pleased that our aggressive financial controls have had a positive impact on our cash flow.``

Simplex will hold a conference call for financial analysts and investors today at 2:00 p.m., PDT and will include a business outlook. A live webcast of the call will be available on Simplex`s Web site at www.simplex.com or at www.videonewswire.com. Following completion of the call, a rebroadcast of the webcast will be available at www.simplex.com or www.videonewswire.com through April 26, 2002. For those without access to the Internet, a replay of the call will be available from 5:00 p.m. PDT on April 18, 2002 through April 26, 2002. To listen to a replay, call 719-457-0820, access code 704508.

Cautionary Note Regarding Forward-looking Statements

This release contains forward-looking statements (including, without limitation, our future quarterly revenue, growth and visibility) that involve risks and uncertainties that could cause the results of Simplex to differ materially from management`s current expectations.

Actual results may differ materially due to a number of factors including, among others: future strategic decisions made by Simplex; competitive developments; demand for advanced semiconductor chips; and the rapid pace of technological change in the semiconductor industry. The matters discussed in this press release also involve risks and uncertainties described in Simplex`s most recent filings with the Securities and Exchange Commission. Simplex assumes no obligation to update the forward-looking information contained in this release.

About Simplex

Simplex Solutions, Inc. provides software and services for the design and verification of integrated circuits (ICs) to enable its communications, computer and consumer-products customers to achieve first-time production success and rapid delivery of complex systems-on-chip. Simplex`s customers use its products and services prior to manufacture to design and verify ICs to help ensure that they will perform as intended, taking into account the complex effects of deep-submicron semiconductor physics. Simplex can be reached at 408-617-6100 or on the web at www.simplex.com.

NOTE: Simplex Solutions, the Simplex logo and SignalStorm are trademarks of Simplex Solutions, Inc.


Simplex Solutions, Inc.
Pro Forma Condensed Consolidated Statements of Operations
(in thousands, except per share data)
(unaudited)

Quarter Ended Six Months Ended
March 31, March 31
2002 2001 2002 2001
Revenue:
Software
Software-License $3,952 $6,191 $9,281 $10,472
Software-Service 2,964 2,312 5,800 4,993
Design foundry 3,000 3,152 5,947 5,364
9,916 11,655 21,028 20,829
Costs of Revenue:
Cost of software -- 24 12 26
Cost of service 485 630 953 1,718
Cost of design 2,098 1,691 4,173 3,039
Total cost of revenue 2,583 2,345 5,138 4,783

Gross Margin 7,333 9,310 15,890 16,046

Expenses:
Selling and marketing 4,569 4,423 8,812 7,541
Research and development 3,931 3,221 7,292 5,458
General and administrative 1,537 1,257 2,826 2,392
10,037 8,901 18,930 15,391

Income/(loss) from operations (2,704) 409 (3,040) 655

Interest and other income 291 24 815 124
Interest expense (23) (129) (24) (240)

Income/(loss) before income taxes (2,436) 304 (2,249) 539

Provision for income taxes 196 135 307 320

Proforma Net Income (Loss) $(2,632) $169 $(2,556) $219

Basic proforma net income/(loss)
per share $(0.17) $0.03 $(0.18) $0.04

Fully diluted proforma net income/(loss)
per share $(0.17) $0.01 $(0.18) $0.02

Number of shares used in calculation of
basic proforma net income/(loss)
per share 15,081 5,611 14,455 5,507
Number of shares used in calculation of
diluted proforma net income/(loss)
per share 15,081 11,609 14,455 11,719


Simplex Solutions, Inc.
Condensed Consolidated Statements of Operations
(in thousands, except per share data)
(unaudited)


Quarter Ended Six Months Ended
March 31, March 31
2002 2001 2002 2001
Revenue:
Software
Software-License $3,952 $6,191 $9,281 $10,472
Software-Service 2,964 2,312 5,800 4,993
Design foundry 3,000 3,152 5,947 5,364
9,916 11,655 21,028 20,829
Costs of Revenue:
Cost of software -- 24 12 26
Cost of service 485 630 953 1,718
Cost of design 2,098 1,691 4,173 3,039
Total cost of revenue 2,583 2,345 5,138 4,783

Gross Margin 7,333 9,310 15,890 16,046

Expenses:
Selling and marketing 4,569 4,423 8,812 7,541
Research and development 3,931 3,221 7,292 5,458
General and administrative 1,537 1,257 2,826 2,392
Amortization of acquired
intangibles 118 1,639 231 3,278
Stock-based compensation 954 1,571 2,009 4,116
-- -- --
11,109 12,111 21,170 22,785

Loss from operations (3,776) (2,801) (5,280) (6,739)

Interest and other income 291 24 815 124
Interest expense (23) (129) (24) (240)

Loss before income taxes (3,508) (2,906) (4,489) (6,855)

Provision for income taxes 196 135 307 320

Net Loss $(3,704) $(3,041) $(4,796) $(7,175)


Basic net loss per share $(0.25) $(0.54) $(0.33) $(1.30)

Number of shares used in calculation
of basic net loss per share 15,081 5,611 14,455 5,507


SIMPLEX SOLUTIONS, INC.
CONDENSED CONSOLIDATED BALANCE SHEET
(in thousands)


March 31, 2002 Sept. 30, 2001

Cash, cash equivalents and short-
term investments 51,329 50,671
Accounts receivable 8,728 17,237
Prepaid expenses and other current
assets 1,199 1,588

Total current assets 61,256 69,496

Property and equipment, net 6,056 5,114
Other assets 437 458
Intangible assets, net 26,831 24,379

Total assets 94,580 99,447



Accounts payable 1,594 1,859
Accrued liabilities 2,185 2,008
Accrued payroll and related expenses 4,754 5,784
Deferred revenue 5,508 7,781
Total current liabilities 14,041 17,432

Other long term liabilities 122 122
Note payable -- 150
Total liabilities 14,163 17,704


Common stock 15 15
APIC 132,422 130,317
Notes receivable from stockholders (1,034) (1,283)
Unearned stock-based compensation (4,716) (6,725)
Accumulated other comprehensive
income (loss) (847) 46
Accumulated deficit (45,423) (40,627)
Total stockholders` equity 80,417 81,743

Total liabilities and
stockholders`equity 94,580 99,447

SOURCE: Simplex Solutions, Inc.

[Chipdesign]

X Initiative and ASML Confirm Manufacturability of X Architecture
Processed Wafers a Manufacturing Milestone for Breakthrough Chip Architecture
SUNNYVALE, Calif., April 21 /PRNewswire-FirstCall/ -- The X Initiative and ASML Netherlands B.V. (Nasdaq: ASML - news) today announced that ASML has successfully produced the first processed wafer results for the X Architecture, a breakthrough chip architecture based on pervasively diagonal chip wiring. The X Initiative, a semiconductor supply-chain consortium chartered with accelerating the availability and fabrication of the X Architecture, announced the addition of ASML to its roster as the first member from the lithography equipment sector.

ASML, one of the world`s leading providers of advanced technology systems for the semiconductor industry, announced that it had simulated lithography performance of 0.18-micron X Architecture design data and successfully completed proof-of-concept wafer exposures of diagonally oriented 0.25-micron interconnect structures based on the 0.18-micron design rules. These first-ever wafer results indicate that interconnect layers can be successfully made using the X Architecture approach and mark a milestone in demonstrating the ability to manufacture X Architecture interconnect designs.

ASML`s experiments, sponsored by the X Initiative and its members, employed X Architecture design data provided by Simplex Solutions, Inc. (Nasdaq: SPLX - news), and photomasks produced by Dai Nippon Printing (DNP). Simulation results -- determined through the use of ASML`s MaskTools LithoCruiser(TM) software -- confirm that existing mask data automation and simulation software can be successfully applied to X Architecture design data to optimize lithographic wafer production results. The interconnect layers were exposed using an ASML PAS 5500/750(TM) DUV step and scan tool.

``Lithography is an especially critical part of the semiconductor manufacturing chain, particularly since the advent of the sub-wavelength era. So naturally, as with any new chip architecture, there have been questions about the impact of the X Architecture on lithography,`` said Risto Puhakka, vice president at VLSI Research. ``The results of ASML`s experiments using current-generation equipment demonstrate that X Architecture designs are both production-worthy and manufacturable.``

``We are pleased to have played a role in demonstrating the manufacturability of the revolutionary X Architecture,`` said Bill Arnold, chief executive scientist and vice president technology development center for ASML. ``We can see the potential benefits of using this approach on non-minimum-resolution interconnect layers, and with our breadth of technology and experience, we are able to provide both mask enhancement and patterning technology to meet the needs of current X Architecture requirements.``

``ASML`s membership brings the critical wafer lithography steps into the X Initiative, heralding a new phase in solidifying supply-chain adoption,`` said Jan Willis, vice president of business development at Simplex and X Initiative steering group facilitator. ``Because the fundamental mission of the X Initiative is to accelerate the availability and fabrication of the X Architecture, the delivery of cost-effective X Architecture masks and wafers is essential to our success. Since ASML was able to use existing equipment and processes in their testing, their positive results represent a significant step forward in accomplishing the X Initiative`s goals.``

Anyone interested in learning more about the X Initiative and the aforementioned results is invited to attend an X Initiative Open Forum seminar on Tuesday, May 21 from 12:00 to 2:00 p.m. PDT at the Fairmont Hotel in San Jose, Calif. The seminar will feature ASML`s Adolph Hunter, manager strategic partnerships. Those interested may RSVP at www.xinitiative.org, where extensive information on the X Architecture is also available.

About ASML

ASML is one of the world`s leading providers of advanced technology systems for the semiconductor industry. The company offers an integrated portfolio of lithography, track and thermal systems mainly for manufacturing complex integrated circuits. Headquartered in Veldhoven, the Netherlands, ASML is traded on the Euronext Amsterdam and on the Nasdaq Stock Market under the symbol ASML. For 2001 the company reported net sales of over EUR 1.8 billion and employs more than 7,000 people in 50 locations throughout the world. For more information, visit: www.asml.com

About the X Architecture

The X Architecture, the first production-worthy approach to the pervasive use of diagonal interconnect, reduces the total interconnect, or wiring, on a chip by more than 20 percent. Based on initial evaluations, this wire-length reduction is expected to deliver simultaneous improvements of 10+ percent greater chip performance, 20+ percent less power dissipation, and 30+ percent more chips per wafer for complex, multiple-metal-layer ICs such as systems-on- chip (SoCs). For the past 20 years, chip design has been primarily based on the de-facto industry standard ``Manhattan`` architecture, named for its right-angle interconnects resembling a city-street grid. The X Architecture rotates the primary direction of the interconnect in the fourth and fifth metal layers by 45 degrees from a Manhattan architecture. The new architecture maintains compatibility with existing cell libraries, memory cells, compilers and IP cores, by preserving the Manhattan geometry of metal layers one through three.

About the X Initiative

The X Initiative, a group of leading companies from throughout the semiconductor industry, is chartered with accelerating the availability and fabrication of the X Architecture, a revolutionary interconnect architecture based on the pervasive use of diagonal routing. The X Initiative`s five-year mission is to provide an independent source of education about the X Architecture, to facilitate support and fabrication of the X Architecture through the semiconductor industry supply chain, and to survey usage of the X Architecture to track its adoption. Representing leaders spanning the entire design-to-silicon infrastructure, X Initiative members include: Artisan Components, Inc.; ASML Netherlands B.V.; Dai Nippon Printing (DNP); DuPont Photomasks, Inc.; Etec Systems, Inc., an Applied Materials, Inc. company; HPL Technologies, Inc.; KLA-Tencor Corporation; Leica Microsystems AG; Matsushita Electric Industrial Co., Ltd.; MicroArk Co. Ltd.; Monterey Design Systems, Inc.; Numerical Technologies, Inc.; NurLogic Design, Inc.; PDF Solutions, Inc.; Photronics, Inc.; Prolific, Inc.; RUBICAD Corporation; Sagantec; Sanyo Electric Co., Ltd.; Silicon Logic Engineering, Inc.; SiliconMap, LLC.; Silicon Perspective Corp.; Silicon Valley Research Inc.; Simplex Solutions, Inc.; STMicroelectronics; Sycon Design, Inc.; Tensilica, Inc.; Toppan Printing Co.; Toshiba Machine Co., Ltd.; Toshiba Corporation; Virage Logic, Inc.; Virtual Silicon Technology, Inc.; and Zygo Corporation. Membership is open to all companies throughout the semiconductor supply chain. Materials can be found at www.xinitiative.org

Cautionary Note Regarding Forward-looking Statements

This release contains forward-looking statements (including, without limitation, information regarding semiconductor design, production and performance improvements resulting from the X Architecture, the compatibility of the X Architecture with current technology, the future success of X Architecture technology and the ability of certain of the X Initiative members` to support the X Architecture) that involve risks and uncertainties that could cause the results of X Initiative members and other events to differ materially from managements` current expectations. Actual results and events may differ materially due to a number of factors including, among others: future strategic decisions made by the X Initiative members; failure of the X Architecture to enable the production of designs that are feasible and competitive with current designs or future alternatives; future strategic decisions made by X Initiative members or others that inhibit the development of the X Architecture; demand for advanced semiconductors that are developed using the X Architecture; cost feasibility of the production of semiconductors designed using the X Architecture; and the rapid pace of technological change in the semiconductor industry. The matters discussed in this press release also involve risks and uncertainties described in the most recent filings of the X Initiative members with the Securities and Exchange Commission. The X Initiative members assume no obligation to update the forward-looking information contained in this release.

NOTE: All trademarks are the property of their respective owners.

SOURCE: X Initiative

[Chipdesign]

Simplex wird übernohmen!




Cadence Expands Technology Leadership at 0.13-Micron-and-Below With Acquisition of Simplex
Cadence Brings Together World-Class Teams and Best-in-Class Technologies
SAN JOSE, Calif., April 24 /PRNewswire-FirstCall/ -- Cadence Design Systems, Inc. (NYSE: CDN - news), the world`s leading supplier of electronic design products and services, today announced it has signed a definitive merger agreement to acquire Simplex Solutions, Inc. (Nasdaq: SPLX - news), a Sunnyvale, California-based company that provides software and services for the design and verification of integrated circuits (ICs). An analyst/press briefing hosted by the CEOs of Cadence and Simplex will begin at 1:45 p.m. (Pacific) and can be accessed at http://www.cadence.com/company/investor_relations." target="_blank" rel="nofollow ugc noopener">http://www.cadence.com/company/investor_relations.

Under the terms of the agreement, Cadence will acquire Simplex in a tax-free, stock-for-stock merger with an equity value of approximately $300 million, or $18 per share of Simplex common stock, at the time of announcement. The acquisition is expected to be completed in the third quarter of 2002.

``Our strategy is to bring the best technology to market for 0.13-micron-and-below design,`` said Ray Bingham, president and CEO of Cadence Design Systems. ``We have been building the solutions for the next generation of IC design for more than a year now. We are executing through our own innovation, accelerated by the acquisition of leading-edge technology from CadMOS, Silicon Perspective Corp. and Plato Design Systems. The proposed acquisition of Simplex fuels our efforts to supply our customers with the world`s best technology to ensure 1st Silicon Success®. Simplex`s world-class technology and management team will be making significant contributions to the combined company.``

``We`re excited by the opportunity to participate in the transformation of Cadence and the electronics industry,`` said Penny Herscher, chairman and CEO of Simplex. ``With Cadence`s strong global channel and technology investment in 0.13-micron and below, together we are able to deliver the best immediate and long-term solutions for our customers` most daunting technology challenges.``

As semiconductor process geometries move to 0.13-micron and below, deep-submicron (DSM) physics create new challenges for the semiconductor industry that require a new generation of design technology solutions. To be successful at these smaller geometries, designers need tools that can easily interoperate, support hierarchical design methods and rapid prototyping, and that take into account critical DSM effects such as signal integrity, voltage (IR) drop, electromigration and substrate noise.

As a leading innovator in the area of DSM system-on-a-chip (SoC) verification solutions, Simplex will provide Cadence with complementary best-in-class technology for 3D parasitic extraction and full-chip power-grid planning, electromigration and signal integrity solutions. Simplex also brings a fast-growing, leading-edge design services capability that specializes in high-performance, multi-million-gate digital designs to complement Cadence`s strengths in leading-edge analog and mixed-signal design. Simplex will also provide Cadence with an exciting opportunity to improve supply chain relationships through the X Initiative, and design performance, power, cost and yield through the X Architecture interconnect technology.

Once the merger is completed, the Simplex leadership team will play key roles in Cadence`s future. Penny Herscher will become executive vice president and chief marketing officer responsible for marketing, strategy, Tality and the Simplex SoC Design Foundry, reporting to Ray Bingham. Aki Fujimura, Simplex president and COO, will become corporate vice president and general manager of the Design for Manufacturability business unit, reporting to Lavi Lev, executive vice president and general manager of the IC business unit. Steve Teig, Simplex chief technology officer, will become the Cadence chief scientist and will join the office of the CTO, reporting to Ray Bingham.

Customers Applaud Merger

``Both Cadence and Simplex products are part of ST`s standard design kit for our advanced 0.13 micron process,`` said Joel Monnier, corporate vice president and central R&D director at ST Microelectronics. ``The addition of the Simplex tools and team, together with its recent acquisition of Silicon Perspective and Plato Design Systems, gives Cadence a complete set of best-in-class solution for 0.13-micron and below.``

``We have worked closely with Simplex on the technology for the X Architecture for more than three years,`` said Dr. Susumu Kohyama, corporate senior vice president, Toshiba Corporation. ``Cadence is also a trusted design technology partner, and we look forward to continuing our collaboration on the X Architecture as the Simplex team becomes part of Cadence.``

Terms of the Merger Agreement

Upon closing of the merger, Simplex stockholders will receive in exchange for each outstanding share of Simplex stock held by them between 0.924 and 0.756 shares of Cadence common stock, depending on the price of Cadence common stock prior to the closing.

The merger of Cadence and Simplex is subject to certain conditions, including compliance with applicable regulatory requirements and the approval by Simplex`s stockholders. As a result of the merger, Simplex will become a wholly owned subsidiary of Cadence.

In connection with the merger agreement, Simplex has issued to Cadence an option to purchase 19.9% of the outstanding shares of Simplex stock for $18 per share. The option will become exercisable under certain circumstances.

About Cadence

Cadence is the largest supplier of electronic design technologies, methodology services, and design services. Cadence solutions are used to accelerate and manage the design of semiconductors, computer systems, networking and telecommunications equipment, consumer electronics, and a variety of other electronics-based products. With approximately 5,600 employees and 2001 revenues of approximately $1.4 billion, Cadence has sales offices, design centers, and research facilities around the world. The company is headquartered in San Jose, California, and traded on the New York Stock Exchange under the symbol CDN. More information about the company, its products and services are available at http://www.cadence.com .

About Simplex

Simplex Solutions, Inc. provides software and services for the design and verification of integrated circuits (ICs) to enable its communications, computer and consumer-products customers to achieve first-time production success and rapid delivery of complex systems-on-chip. Simplex`s customers use its products and services prior to manufacture to design and verify ICs to help ensure that they will perform as intended, taking into account the complex effects of deep-submicron semiconductor physics. Simplex can be reached at 408-617-6100 or on the web at http://www.simplex.com .

Additional Information about the Proposed Merger and Where to Find It

Cadence Design Systems, Inc. and Simplex Solutions, Inc. intend to file with the Securities and Exchange Commission a registration statement, including a proxy statement/prospectus, and other relevant materials in connection with the proposed merger. The proxy statement/prospectus will be mailed to the stockholders of Simplex. Investors and security holders of Simplex are urged to read the proxy statement/prospectus and the other relevant materials when they become available because they will contain important information about Cadence, Simplex and the proposed merger. The proxy statement/prospectus and other relevant materials (when they become available), and any other documents filed by Cadence or Simplex with the Securities and Exchange Commission, may be obtained free of charge at the Securities and Exchange Commission`s web site at www.sec.gov. In addition, investors and security holders may obtain free copies of the documents filed with the Securities and Exchange Commission by Cadence by contacting Cadence Investor Relations, 2655 Seely Avenue, Building 5, San Jose, California 95134, 408-943-1234. Investors and security holders may obtain free copies of the documents filed with the Securities and Exchange Commission by Simplex by contacting Simplex Investor Relations, 521 Almanor Avenue, Sunnyvale, California 94085, 408-617-6100. Investors and security holders are urged to read the joint proxy statement/prospectus and the other relevant materials when they become available before making any voting or investment decision with respect to the proposed merger.

Simplex and its executive officers and directors may be deemed to be participants in the solicitation of proxies from the stockholders of Simplex in favor of the proposed merger. A description of the interests of the executive officers and directors in Simplex is set forth in the proxy statement for Simplex`s 2002 Annual Meeting of Stockholders, which was filed with the Securities and Exchange Commission on January 10, 2002. This document is available free of charge at the Securities and Exchange Commission`s web site at www.sec.gov and from Simplex by directing a request to Simplex Investor Relations, 521 Almanor Avenue, Sunnyvale, California 94085, 408-617-6100. Investors and security holders may obtain more detailed information regarding the direct and indirect interests of the executive officers and directors in the proposed merger by reading the joint proxy statement/prospectus when it becomes available.

Cautionary Note Regarding Forward-Looking Statements

This press release contains forward-looking statements within the meaning of the federal securities laws, including, without limitation, statements regarding the following: the proposed merger between Cadence and Simplex and the potential benefits and opportunities relating to the proposed merger; strategies, beliefs and expectations regarding technologies, products, services and solutions; the electronics and semiconductor industries; and the integration of the Simplex leadership team. These statements are subject to risks and uncertainties that could cause actual results and events to differ materially, including, without limitation, the following: the approval of the proposed merger by Simplex`s stockholders; the satisfaction of closing conditions, including the receipt of regulatory approvals; the successful integration of Simplex`s employees and technologies; the rapid pace of technological change in the electronics and semiconductor industries; fluctuations in the demand for Cadence`s and Simplex`s products, services and solutions; possible development or marketing delays relating to product offerings; and the introduction of new products by competitors or the entry of new competitors into the markets for Cadence`s and Simplex`s products. A detailed discussion of other risks and uncertainties that could cause actual results and events to differ materially from such forward-looking statements is included in Cadence`s and Simplex`s most recent filings with the Securities and Exchange Commission. Neither Cadence nor Simplex undertakes any obligation to update forward-looking statements to reflect events or circumstances occurring after the date of this press release.

NOTE: 1st Silicon Success is a registered trademark and Simplex Solutions and the Simplex logo are trademarks of Simplex Solutions, Inc. Cadence and the Cadence logo are registered trademarks of Cadence Design Systems, Inc. All other trademarks are the property of their respective owners.

SOURCE: Simplex Solutions, Inc.